mc68hc05p9a Freescale Semiconductor, Inc, mc68hc05p9a Datasheet
mc68hc05p9a
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mc68hc05p9a Summary of contents
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... Freescale Semiconductor, Inc For More Information On This Product, MC68HC05P9A HCMOS Microcontroller Unit Go to: www.freescale.com MC68HC05P9A/D TECHNICAL DATA ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Central Processor Unit (CPU Resets and Interrupts Low-Power Modes Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . 65 Computer Operating Properly Watchdog (COP Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Serial Input/Output Port (SIOP 103 Analog-to-Digital Converter (ADC 117 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Index 141 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . 153 ...
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... Freescale Semiconductor, Inc. List of Sections 4 For More Information On This Product, List of Sections Go to: www.freescale.com MOTOROLA ...
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... Freescale Semiconductor, Inc. Introduction Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mask Selectable Options .12 Pin Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Functions .15 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 RAM .24 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ROM Security Feature .24 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 CPU Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CPU Control Unit ...
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... Freescale Semiconductor, Inc. Table of Contents Resets Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 and Interrupts Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Low-Power Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Port .67 Port .70 Port .73 Port .76 COP Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Operation .80 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Low-Power Modes .82 Timer Contents ...
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... Freescale Semiconductor, Inc. SIOP Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Operation .106 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Low-Power Modes .116 ADC Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Operation .119 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .121 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Low-Power Modes .125 Specifications Contents ...
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... Freescale Semiconductor, Inc. Table of Contents Index Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Literature Updates Literature Distribution Centers .153 Mfax .154 Motorola SPS World Marketing World Wide Web Server . . . . . . . . .154 CSIC Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . .154 8 For More Information On This Product, Table of Contents Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mask Selectable Options .12 1-mc68hc05p9a MOTOROLA For More Information On This Product, Introduction Go to: www.freescale.com Introduction 9 ...
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... Bytes of ROM – 48 Bytes of Page Zero ROM – Eight Locations for User Vectors – ROM Security 128 Bytes of User RAM Selfcheck ROM Memory-Mapped Input/Output (I/O) Registers Fully Static Operation with No Minimum Clock Speed Power-Saving Stop and Wait Modes Introduction Go to: www.freescale.com 2-mc68hc05p9a MOTOROLA ...
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... PROGRAM COUNTER OSC1 INTERNAL OSCILLATOR OSC2 COP WATCHDOG V DD POWER V SS Figure 1. MC68HC05P9A Block Diagram 3-mc68hc05p9a MOTOROLA For More Information On This Product, ARITHMETIC/LOGIC UNIT ACCUMULATOR INDEX REGISTER CONDITION CODE REGISTER CPU CLOCK TO ADC INTERNAL CLOCK DIVIDE ...
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... Table 2. User Selectable Mask Options Feature Enabled or Disabled Negative-Edge Triggering Only or Negative-Edge and Low-Level Triggering MSB First or LSB First Enabled Pin-by-Pin or Disabled Pin-by-Pin Enabled or Disabled (Convert to HALT) Introduction Go to: www.freescale.com Order Number MC68HC05P9AP MC68HC05P9ACP MC68HC05P9AVP MC68HC05P9AMP MC68HC05P9ADW MC68HC05P9ACDW MC68HC05P9AVDW MC68HC05P9AMDW Option 4-mc68hc05p9a MOTOROLA ...
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... OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . .16 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 RESET IRQ PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PB7/SCK–PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PC7/V PD7/TCAP and PD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5-mc68hc05p9a MOTOROLA For More Information On This Product, and . . .17 –PC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 RH Pin Descriptions Go to: www.freescale.com Pin Descriptions ...
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... IRQ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5/SDO PB6/SDI PB7/SCK For More Information On This Product, Figure 2. Pin Assignments Pin Descriptions Go to: www.freescale.com V DD OSC1 OSC2 PD7/TCAP TCMP PD5 PC0 PC1 PC2 PC3/AN3 PC4/AN2 PC5/AN1 PC6/AN0 PC7/V RH 6-mc68hc05p9a MOTOROLA ...
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... The frequency of the on-chip oscillator is f internal oscillator output by two to produce the internal clock with a frequency of f 7-mc68hc05p9a MOTOROLA For More Information On This Product, are the power supply and ground pins. The MCU operates SS shows. Place the Crystal ...
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... For More Information On This Product, Figure 4 shows a Figure 4. Crystal Connections shows a ceramic Figure 5. Ceramic Resonator Pin Descriptions Go to: www.freescale.com MCU 10 M XTAL MCU CERAMIC RESONATOR Connections 8-mc68hc05p9a MOTOROLA ...
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... The RESET pin input circuit contains an internal Schmitt trigger to improve noise immunity. IRQ The IRQ pin has the following functions: • • 9-mc68hc05p9a MOTOROLA For More Information On This Product, Figure 6. The shows. Applying asynchronous external interrupt signals Applying V , the mode detection voltage ...
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... Port 2-pin I/O port that shares one of its pins with the capture/compare timer. Use data direction register D to configure port D pins as inputs or outputs. TCMP The TCMP pin is the output compare pin for the capture/compare timer. 18 For More Information On This Product, Pin Descriptions Go to: www.freescale.com 10-mc68hc05p9a MOTOROLA ...
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... ROM Security Feature .24 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Features • 2104 Bytes of ROM – 48 Bytes of Page Zero ROM – Eight Locations for User Vectors • 128 Bytes of User RAM • 240 Selfcheck ROM 5-mc68hc05p9a MOTOROLA For More Information On This Product, Memory Go to: www.freescale.com Memory 19 ...
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... Reserved $001F $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF 6-mc68hc05p9a MOTOROLA ...
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... Data Direction Register A (DDRA) $0004 Data Direction Register B (DDRB) $0005 Data Direction Register C (DDRC) $0006 Data Direction Register D (DDRD) $0007 Unimplemented $0008 Unimplemented $0009 7-mc68hc05p9a MOTOROLA For More Information On This Product, R/W Bit Read: PA7 PA6 PA5 Write: Reset: Read: ...
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... Reset: Unaffected by reset = Unimplemented R Memory Go to: www.freescale.com Bit Bit IEDG OLVL Bit Bit Bit 8 = Reserved U = Unaffected 8-mc68hc05p9a MOTOROLA ...
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... Alternate Timer Register Low (ATRL) $001B Unimplemented $001C ADC Data Register (ADDR) $001D ADC Status/Control Register (ADSCR) $001E Reserved $001F $1FF0 COP Register (COPR) Figure 9. I/O Register Summary (Continued) 9-mc68hc05p9a MOTOROLA For More Information On This Product, R/W Bit Read: Bit ...
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... No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the ROM difficult for unauthorized users. 24 For More Information On This Product, $0020–$004F $0100–$08FF $1FF8–$1FFF (reserved for user-defined interrupt and reset vectors) 1 feature has been incorporated into the MC68HC05P9A to Memory Go to: www.freescale.com 10-mc68hc05p9a MOTOROLA ...
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... Self-check results (using LEDs as monitors) are shown in Table self-check code. The self-check code is subject to change at any time to improve testability or manufacturability. 11-mc68hc05p9a MOTOROLA For More Information On This Product not recommended that the user code use any of the Table 3. Self-Check Results ...
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... PA3 PC0 7 22 PA2 PC1 8 21 PA1 PC2 9 20 PA0 PC3 10 19 SDO/PB5 PC4 11 18 SDI/PB6 PC5 12 17 SCK/PB7 PC6 PC7 14 15 Figure 10. Self-Check Circuit Memory Go to: www.freescale.com MHz 470 10 K 12-mc68hc05p9a MOTOROLA ...
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... Freescale Semiconductor, Inc. Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 CPU Registers .30 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Register/Memory Instructions ...
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... Freescale Semiconductor, Inc. CPU Features • • • • • • • • • Introduction The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. ...
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... Freescale Semiconductor, Inc 7-hc05cpu MOTOROLA For More Information On This Product, CPU CONTROL UNIT ...
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... Freescale Semiconductor, Inc. CPU CPU Control Unit The CPU control unit fetches and decodes instructions during program operation. The control unit selects the memory locations to read and write and coordinates the timing of all CPU operations. Arithmetic/Logic Unit The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the CPU control unit ...
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... Freescale Semiconductor, Inc. Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic and logic operations. Read: Write: Reset: Index Register The index register can be used for data storage counter. In the indexed addressing modes, the CPU uses the byte in the index register to determine the effective address of the operand ...
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... Freescale Semiconductor, Inc. CPU The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations ...
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... Freescale Semiconductor, Inc. H — Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. I — Interrupt Mask Setting the interrupt mask disables interrupts interrupt request ...
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... Freescale Semiconductor, Inc. CPU Instruction Set The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X) ...
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... Freescale Semiconductor, Inc. Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. ...
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... Freescale Semiconductor, Inc. CPU Indexed, Indexed, 16-bit offset instructions are 3-byte instructions that can access 16-Bit Offset data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. ...
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... Freescale Semiconductor, Inc. Instruction Types The MCU instructions fall into the following five categories: • • • • • Register/ These instructions operate on CPU registers and memory locations. Memory Most of them use two operands. One operand is in either the Instructions accumulator or the index register. The CPU finds the other operand in memory ...
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... Freescale Semiconductor, Inc. CPU Read-Modify- These instructions read a memory location or a register, modify its Write Instructions contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. 38 For More Information On This Product, Table 5 ...
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... Freescale Semiconductor, Inc. Jump/Branch Jump instructions allow the CPU to interrupt the normal sequence of the Instructions program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...
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... Freescale Semiconductor, Inc. CPU 40 For More Information On This Product, Table 6. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High ...
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... Freescale Semiconductor, Inc. Bit Manipulation The CPU can set or clear any writable bit in the first 256 bytes of Instructions memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. ...
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... Freescale Semiconductor, Inc. CPU Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ADC opr ,X ADC opr ,X ADC ,X ADD # opr ADD opr ADD opr Add without Carry ADD opr ,X ADD opr ,X ADD ,X AND # opr AND opr ...
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... Freescale Semiconductor, Inc. Table 9. Instruction Set Summary (Continued) Source Operation Form BHI rel Branch if Higher BHS rel Branch if Higher or Same BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT # opr BIT opr BIT opr Bit Test Accumulator with Memory Byte ...
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... Freescale Semiconductor, Inc. CPU Table 9. Instruction Set Summary (Continued) Source Operation Form BSR rel Branch to Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr CMP opr CMP opr Compare Accumulator with Memory Byte ...
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... Freescale Semiconductor, Inc. Table 9. Instruction Set Summary (Continued) Source Operation Form JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X JSR ,X LDA # opr LDA opr LDA opr Load Accumulator with Memory Byte ...
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... Freescale Semiconductor, Inc. CPU Table 9. Instruction Set Summary (Continued) Source Operation Form ROL opr ROLA ROLX Rotate Byte Left through Carry Bit ROL opr ,X ROL ,X ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr ,X ROR ,X RSP Reset Stack Pointer ...
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... Freescale Semiconductor, Inc. Table 9. Instruction Set Summary (Continued) Source Operation Form SWI Software Interrupt TAX Transfer Accumulator to Index Register TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr ,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts ...
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... Freescale Semiconductor, Inc. 48 For More Information On This Product, CPU CPU Go to: www.freescale.com 26-hc05cpu MOTOROLA ...
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... Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5-mc68hc05p9a MOTOROLA For More Information On This Product, Resets and Interrupts Resets and Interrupts Go to: www.freescale.com 49 ...
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... INTERNAL CLOCK Figure 17. Reset Sources pin generates a power-on reset. DD (internal clock cycle) delay after the oscillator becomes CYC , the MCU remains in the reset condition until CYC Resets and Interrupts Go to: www.freescale.com RST S TO CPU AND D Q SUBSYSTEMS CK RESET LATCH 6-mc68hc05p9a MOTOROLA ...
Page 51
... NOTES: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. RESET Pulse Width 7-mc68hc05p9a MOTOROLA For More Information On This Product ...
Page 52
... RESET pin low when it detects a low-power supply voltage. The undervoltage sensing circuit may be made of discrete components or an integrated circuit can be used. For information about brownout and the COP watchdog, see the Computer Operating Properly Watchdog 52 For More Information On This Product, Resets and Interrupts Go to: www.freescale.com DD section. 8-mc68hc05p9a MOTOROLA ...
Page 53
... IRQ pin can latch another interrupt request during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. 9-mc68hc05p9a MOTOROLA For More Information On This Product, SWI instruction ...
Page 54
... For More Information On This Product, EDGE AND LEVEL Figure 21, is latched as long as any source is holding t ILIL t PIN ILIH PP t IRQ ILIH IRQ n Figure 21. External Interrupt Timing Resets and Interrupts Go to: www.freescale.com EDGE ONLY EXTERNAL INTERRUPT REQUEST I BIT (FROM CCR) 10-mc68hc05p9a MOTOROLA ...
Page 55
... An output compare interrupt request occurs if the output compare flag, Interrupt OCF, becomes set while the output compare interrupt enable bit, OCIE, is also set. OCF is in the timer status register, and OCIE is in the timer control register. 11-mc68hc05p9a MOTOROLA For More Information On This Product, Table 12. External Interrupt Timing (V Characteristic = 5 ...
Page 56
... Loads the program counter with the contents of the appropriate interrupt vector locations: – $1FFC and $1FFD (software interrupt vector) – $1FFA and $1FFB (external interrupt vector) – $1FF8 and $1FF9 (timer interrupt vector) Resets and Interrupts Go to: www.freescale.com Figure 22. 12-mc68hc05p9a MOTOROLA ...
Page 57
... Freescale Semiconductor, Inc. STACKING ORDER Function Reset Software Interrupt (SWI) External Interrupt Timer Interrupts 1. The COP watchdog is a mask option. 13-mc68hc05p9a MOTOROLA For More Information On This Product, • UNSTACKING ORDER • • CONDITION CODE REGISTER 4 2 ACCUMULATOR 3 3 INDEX REGISTER ...
Page 58
... EXTERNAL CLEAR IRQ LATCH. INTERRUPT? NO TIMER YES INTERRUPT? STACK PC CCR. NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CCR PC. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 23. Interrupt Flowchart Resets and Interrupts Go to: www.freescale.com SET I BIT. 14-mc68hc05p9a MOTOROLA ...
Page 59
... An external interrupt signal on the IRQ pin or a high-to-low transition on the IRQ pin loads the program counter with the contents of locations $1FFA and $1FFB. The timer resumes counting from the last value before the STOP instruction. 5-mc68hc05p9a MOTOROLA For More Information On This Product, Low-Power Modes Low-Power Modes Go to: www ...
Page 60
... The timer begins counting from $FFFC. for stop recovery timing information ILIH PP 4064 t CYC 1FFE 1FFE (NOTE 4) Figure 24. Stop Recovery Timing Low-Power Modes Go to: www.freescale.com 1FFE 1FFE 1FFE 1FFF RESET OR INTERRUPT VECTOR FETCH 6-mc68hc05p9a MOTOROLA ...
Page 61
... Figure 25 instruction. 7-mc68hc05p9a MOTOROLA For More Information On This Product, shows the sequence of events caused by the STOP/HALT Low-Power Modes Go to: www.freescale.com ...
Page 62
... RESTART EXTERNAL OSCILLATOR, START STABILIZATION DELAY Y END Y OF STABILIZATION DELAY? N RESTART INTERNAL PROCESSOR CLOCK 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Low-Power Modes Go to: www.freescale.com HALT AND EXTERNAL RESET? N IRQ N TIMER INTERNAL N COP INTERNAL RESET? N 8-mc68hc05p9a MOTOROLA ...
Page 63
... Figure 26 instruction. Figure 27 CPU clock and the timer clock. 9-mc68hc05p9a MOTOROLA For More Information On This Product, Clears the I bit in the condition code register, enabling interrupts Stops the CPU clock, but allows the internal clock to drive the capture/compare timer, the COP watchdog, and the ADC External interrupt — ...
Page 64
... SET I BIT IN CCR c. VECTOR TO INTERRUPT SERVICE ROUTINE Figure 26. WAIT Instruction Flowchart WAIT STOP INTERNAL CLOCK 2 OSC1 INTERNAL OSCILLATOR OSC2 2 Figure 27. STOP/WAIT Clock Logic Low-Power Modes Go to: www.freescale.com NO EXTERNAL INTERRUPT? NO TIMER INTERRUPT? NO OTHER ON-CHIP INTERRUPT SOURCES? NO CPU CLOCK TIMER CLOCK ADC CLOCK 10-mc68hc05p9a MOTOROLA ...
Page 65
... Data Direction Register B (DDRB .71 Port .73 Port C Data Register (PORTC .73 Data Direction Register C (DDRC .74 PC0–PC1 High Current Sink/Source Capability . . . . . . . . . . . . . . .75 Port .76 Port D Data Register (PORTD .76 Data Direction Register D (DDRD .77 5-mc68hc05p9a MOTOROLA For More Information On This Product, Parallel I/O Ports Parallel I/O Ports Go to: www.freescale.com 65 ...
Page 66
... DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset Read: 0 DDRB7 DDRB6 DDRB5 Write: Reset Unimplemented Parallel I/O Ports Go to: www.freescale.com Bit 0 PA3 PA2 PA1 PA0 PC3 PC2 PC1 PC0 6-mc68hc05p9a MOTOROLA ...
Page 67
... Read: Write: Reset: PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. 7-mc68hc05p9a MOTOROLA For More Information On This Product, R/W Bit ...
Page 68
... I/O Pin Mode 0 Input, Hi-Z 1 Output 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input. Parallel I/O Ports Go to: www.freescale.com Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 summarizes the operation Accesses to Data Bit Read Write (1) (2) Pin Latch Latch Latch 8-mc68hc05p9a MOTOROLA ...
Page 69
... READ $0004 WRITE $0004 RESET WRITE $0000 READ $0000 SOFTWARE CONTROLLED OPTION FROM OTHER PORT A PINS IRQ RESET EXTERNAL INTERRUPT VECTOR FETCH 9-mc68hc05p9a MOTOROLA For More Information On This Product, V DISABLED MASK OPTION ENABLED DATA DIRECTION REGISTER A BIT DDRA7 PORT A DATA REGISTER ...
Page 70
... For More Information On This Product, External Interrupt on page 53.) Bit PB7 PB6 PB5 Unaffected by reset SCK SDI SDO = Unimplemented Figure 32. Port B Data Register (PORTB) Parallel I/O Ports Go to: www.freescale.com Bit 10-mc68hc05p9a MOTOROLA ...
Page 71
... These read/write bits control port B data direction. Reset clears DDRB[7:5], configuring all three port B pins as inputs. NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from Figure 34 11-mc68hc05p9a MOTOROLA For More Information On This Product, Bit ...
Page 72
... Table 16. Port B Pin Operation Data Direction Bit I/O Pin Mode 0 Input, Hi-Z 1 Output 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input. Parallel I/O Ports Go to: www.freescale.com DDRBx PBx summarizes the operation Accesses to Data Bit Read Write (1) (2) Pin Latch Latch Latch 12-mc68hc05p9a MOTOROLA PBx ...
Page 73
... Unused analog inputs can be used as digital inputs, but pins PC3/AN3, PC4/AN2, PC5/AN1, and PC6/AN0 cannot be used as digital outputs while the ADC is on. Only pins PC0, PC1, and PC2 can be used as digital outputs when the ADC is on. 13-mc68hc05p9a MOTOROLA For More Information On This Product, Bit 7 6 ...
Page 74
... ADC results. Figure 37 74 For More Information On This Product, Bit DDRC7 DDRC6 DDRC5 DDRC4 Figure 36. Data Direction Register C (DDRC) shows the I/O logic of port C. Parallel I/O Ports Go to: www.freescale.com Bit 0 DDRC3 DDRC2 DDRC1 DDRC0 14-mc68hc05p9a MOTOROLA ...
Page 75
... PC0–PC1 High The outputs for the lower two bits of port C (PC0–PC1) can source/sink Current relatively high current. (See Sink/Source page 130 and Capability details.) 15-mc68hc05p9a MOTOROLA For More Information On This Product, DDRCx RESET PCx Figure 37. Port C I/O Logic Table 16 Table 17. Port C Pin Operation ...
Page 76
... TCAP — Timer Capture TCAP is the input capture pin for the timer. 76 For More Information On This Product, Bit PD7 0 1 PD5 Unaffected by reset TCAP = Unimplemented Figure 38. Port D Data Register (PORTD) Parallel I/O Ports Go to: www.freescale.com Bit 16-mc68hc05p9a MOTOROLA ...
Page 77
... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 40 Writing a logic DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. 17-mc68hc05p9a MOTOROLA For More Information On This Product, Bit 7 6 ...
Page 78
... Table 18. Port D Pin Operation Data Direction Bit I/O Pin Mode (1) 0 Input, Hi-Z 1 Output 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input. Parallel I/O Ports Go to: www.freescale.com summarizes the operation Accesses to Data Bit Read Write (2) Pin Latch Latch Latch 18-mc68hc05p9a MOTOROLA ...
Page 79
... Freescale Semiconductor, Inc. Computer Operating Properly Watchdog Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Operation .80 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Low-Power Modes .82 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Features • Protection from runaway software • 131,072/f • ...
Page 80
... Freescale Semiconductor, Inc. COP Introduction The purpose of the computer operating properly (COP) watchdog is to reset the MCU in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents the reset from occurring. The COP watchdog function is selectable with a mask option ...
Page 81
... Freescale Semiconductor, Inc. Clearing the COP To clear the COP watchdog and prevent a COP reset, write a logic 0 to Watchdog bit 0 (COPC) of the COP register at location $1FF0. If the main program executes within the COP timeout period, the clearing routine needs to be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once ...
Page 82
... Freescale Semiconductor, Inc. COP Low-Power Modes The STOP, HALT, and WAIT instructions put the MCU in low-power consumption standby modes. Stop Mode The STOP instruction clears the COP watchdog counter. Upon exit from stop mode by external reset: • • Upon exit from stop mode by external interrupt: • ...
Page 83
... Freescale Semiconductor, Inc. Wait Mode The COP watchdog continues to operate normally after a WAIT instruction. Software should periodically take the MCU out of wait mode and write to the COPC bit to prevent a COP watchdog timeout. MOTOROLA For More Information On This Product, COP Go to: www.freescale.com ...
Page 84
... Freescale Semiconductor, Inc. COP 84 For More Information On This Product, COP Go to: www.freescale.com MOTOROLA ...
Page 85
... Freescale Semiconductor, Inc. Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Operation .89 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Low-Power Modes .102 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Wait Mode ...
Page 86
... Freescale Semiconductor, Inc. Timer Features • • • • • Introduction The timer provides a timing reference for MCU operations. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. ...
Page 87
... Freescale Semiconductor, Inc. EDGE SELECT/ TCAP DETECT LOGIC IEDG INTERNAL CLOCK (XTAL 2) 4 INTERNAL DATA BUS 7-tim1ic1oc_a MOTOROLA For More Information On This Product, ICRH ICRL TRH TRL 16-BIT COUNTER 16-BIT COMPARATOR OCRH OCRL TIMER OVERFLOW OCIE OCF TOIE TOF ICIE ICF Figure 42 ...
Page 88
... Freescale Semiconductor, Inc. Timer Addr. Name $0012 Timer Control Register (TCR) $0013 Timer Status Register (TSR) $0014 Input Capture Register High (ICRH) $0015 Input Capture Register Low (ICRL) $0016 Output Compare Register High (OCRH) $0017 Output Compare Register Low (OCRL) $0018 ...
Page 89
... Freescale Semiconductor, Inc. Operation The timing reference for the input capture and output compare functions is a 16-bit free-running counter. The counter is preceded by a divide-by- four prescaler and rolls over every 2 MHz crystal Software can read the value in the counter at any time without affecting the counter sequence ...
Page 90
... Freescale Semiconductor, Inc. Timer Output Compare The output compare function is a means of generating an output signal when the 16-bit counter reaches a selected value. Software writes the selected value into the output compare registers. On every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers ...
Page 91
... Freescale Semiconductor, Inc. Timing Timer Resolution Input Capture Pulse Width Input Capture Pulse Period 2-bit prescaler in the timer is the limiting factor as it counts The minimum t plus 19 t Timer Resolution Input Capture Pulse Width Input Capture Pulse Period ...
Page 92
... Freescale Semiconductor, Inc. Timer INTERNAL BUS CLOCK INTERNAL TIMER CLOCKS COUNTER RESET (EXTERNAL OR END OF POR) BUS CLOCK TIMER CLOCKS INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE INPUT CAPTURE NOTE: If the input capture edge occurs in the shaded area between T10 states, then the input capture fl ...
Page 93
... Freescale Semiconductor, Inc. BUS CLOCK TIMER CLOCKS OUTPUT COMPARE REGISTERS REGISTER LATCH OUTPUT COMPARE FLAG AND TCMP NOTES write to the output compare registers may occur at any time, but a compare only occurs at timer state T01. Therefore, the compare may follow the write four cycles. ...
Page 94
... Freescale Semiconductor, Inc. Timer Interrupts The following timer sources can generate interrupts: • • • Table 21 I/O Registers The following registers control and monitor the operation of the timer: • • • • • • 94 For More Information On This Product, Input capture flag (ICF) — The ICF bit is set when an edge of the selected polarity occurs on the input capture pin ...
Page 95
... Freescale Semiconductor, Inc. Timer Control The timer control register (TCR) performs the following functions: Register • • • • • $0012 Read: Write: Reset: ICIE — Input Capture Interrupt Enable This read/write bit enables interrupts caused by an active signal on the PD7/TCAP pin. Reset clears the ICIE bit. ...
Page 96
... Freescale Semiconductor, Inc. Timer IEDG — Input Edge The state of this read/write bit determines whether a positive or negative transition on the PD7/TCAP pin triggers a transfer of the contents of the timer registers to the input capture registers. Reset has no effect on the IEDG bit Positive edge (low-to-high transition) triggers input capture 0 = Negative edge (high-to-low transition) triggers input capture OLVL — ...
Page 97
... Freescale Semiconductor, Inc. ICF — Input Capture Flag The ICF bit is automatically set when an edge of the selected polarity occurs on the PD7/TCAP pin. Clear the ICF bit by reading the timer status register with ICF set, and then reading the low byte of the input capture registers. Reset has no effect on ICF. OCF — ...
Page 98
... Freescale Semiconductor, Inc. Timer Timer Registers The read-only timer registers (TRH and TRL) contain the current high and low bytes of the 16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer registers has no effect ...
Page 99
... Freescale Semiconductor, Inc. Alternate Timer The read-only alternate timer registers (ATRH and ATRL) contain the Registers current high and low bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL is read. Reading does not affect the timer overflow flag (TOF). Writing to the alternate timer registers has no effect ...
Page 100
... Freescale Semiconductor, Inc. Timer Input Capture When a selected edge occurs on the TCAP pin, the current high and low Registers bytes of the 16-bit counter are latched into the read-only input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits further captures until ICRL is read. Reading ICRL after reading the timer status register clears the input capture flag (ICF) ...
Page 101
... Freescale Semiconductor, Inc. Output Compare When the value of the 16-bit counter matches the value in the read/write Registers output compare registers (OCRH and OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after reading the timer status register clears the output compare flag (OCF) ...
Page 102
... Freescale Semiconductor, Inc. Timer Low-Power Modes The STOP and WAIT instructions put the MCU in low-power consumption standby modes. Stop Mode The STOP instruction suspends the timer counter. Upon exit from stop mode by external reset: • • Upon exit from stop mode by external interrupt: • ...
Page 103
... Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Low-Power Modes .116 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 5-mc68hc05p9a MOTOROLA For More Information On This Product, Serial Input/Output Port SIOP Go to: www.freescale.com SIOP 103 ...
Page 104
... Master or Slave Operation Programmable MSB-First or LSB-First Operation Interrupt-Driven Operation with Transfer Complete Flag Data Collision Flag Master Mode Frequency = Bus Frequency Maximum Slave Mode Frequency = Bus Frequency No Minimum Slave Mode Frequency shows the structure of the SIOP module. SIOP Go to: www.freescale.com 4 4 6-mc68hc05p9a MOTOROLA ...
Page 105
... CONTROL INTERNAL DIVIDE CLOCK (f 2) OSC Addr. Name $000A SIOP Control Register (SCR) $000B SIOP Status Register (SSR) $000C SIOP Data Register (SDR) 7-mc68hc05p9a MOTOROLA For More Information On This Product, INTERNAL BUS SIOP DATA REGISTER SPE MSTR ...
Page 106
... The direction of serial data does not automatically switch as on the SPI because the SIOP is not intended for use in multimaster systems. Most applications use one MCU as the master to initiate and control data transfer between one or more slave peripheral devices. SIOP Go to: www.freescale.com 8-mc68hc05p9a MOTOROLA ...
Page 107
... In slave mode, the PB7/SCK pin is an input. The maximum serial clock frequency in slave mode is one-fourth the internal clock rate. Slave mode has no minimum serial clock frequency. 9-mc68hc05p9a MOTOROLA For More Information On This Product, PB7/SCK ...
Page 108
... DATA OUTPUT LSB BIT 1 BIT 2 Figure 61. SIOP Data/Clock Timing , before the rising edge of the serial clock and S Table 22 and Table SIOP Go to: www.freescale.com BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 3 BIT 4 BIT 5 BIT 6 MSB , after the rising edge of the H 23.) 10-mc68hc05p9a MOTOROLA ...
Page 109
... SIOP data register on its PB5/SDO pin. At the same time, the slave MCU shifts out the contents of its SIOP data register on its PB5/SDO pin. master and slave exchange the contents of their data registers. 11-mc68hc05p9a MOTOROLA For More Information On This Product, SDO ...
Page 110
... Unit MHz ( ) SIOP M OSC OSC kHz ( ) SIOP S OSC (2) t 4.0 4 SCK M CYC t — 1920 SCK S t 932 — ns SCKL t — 200 — 100 — 100 — unless otherwise noted 12-mc68hc05p9a MOTOROLA LSB ...
Page 111
... SDI Setup Time SDI Hold Time CYC 3. f OSC 4. In master mode, the frequency of SCK is f Interrupts The SIOP does not generate interrupt requests. 13-mc68hc05p9a MOTOROLA For More Information On This Product, Table 23. SIOP Timing (V Characteristic (3) (4) = 1.0 MHz 3.3 Vdc 10 Vdc ...
Page 112
... MSTR Unimplemented Figure 64. SIOP Control Register (SCR) The PB6/SDI pin is an input. The PB5/SDO pin is an output. The PB7/SCK pin is an input in slave mode and an output in master mode. SIOP Go to: www.freescale.com Bit 14-mc68hc05p9a MOTOROLA ...
Page 113
... This read/write bit configures the SIOP for master mode. Setting MSTR initializes the PB7/SCK pin as the serial clock output. Clearing MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can be set at any time regardless of the state of SPE. Reset clears MSTR. 15-mc68hc05p9a MOTOROLA For More Information On This Product SIOP enabled ...
Page 114
... SIOP data register. Reset clears SPIF Transmission complete 0 = Transmission not complete 114 For More Information On This Product, Bit SPIF DCOL Unimplemented Figure 65. SIOP Status Register (SSR) SIOP Go to: www.freescale.com Bit 16-mc68hc05p9a MOTOROLA ...
Page 115
... This register is not buffered. Writing to the SIOP data register overwrites the previous contents. Reading or writing to the SIOP data register while a transmission is in progress can cause invalid data to be transmitted or received. 17-mc68hc05p9a MOTOROLA For More Information On This Product Invalid access of SDR ...
Page 116
... Wait Mode The WAIT instruction suspends the clock to the SIOP. When the MCU exits wait mode, processing resumes immediately. A WAIT instruction in a master SIOP does not suspend the clock to slave SIOPs. 116 For More Information On This Product, SIOP Go to: www.freescale.com 18-mc68hc05p9a MOTOROLA ...
Page 117
... Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Features • 8-Bit Conversions with • Four External and Three Internal Analog Input Channels • Wait Mode Operation 5-mc68hc05p9a MOTOROLA For More Information On This Product, Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 RH 1.5-LSB Precision ADC Go to: www.freescale.com ADC ...
Page 118
... For More Information On This Product, Figure 67 shows the structure of the AN3 COMPARATOR AN2 INPUT MULTIPLEXER AN1 AN1 CH2 CH1 CH0 DIGITAL TO-ANALOG V CONVERTER SS CCF ADON CONTROL LOGIC INTERNAL CLOCK (XTAL 2) INTERNAL RC ADRC OSCILLATOR Figure 67. ADC Block Diagram ADC Go to: www.freescale.com 6-mc68hc05p9a MOTOROLA ...
Page 119
... The ADC uses five pins and shares them with port C: • • PC7/V The voltage reference high pin (PC7/V RH voltage for the ratiometric conversion process. For ratiometric conversion, the supply voltage of the analog source should be the same 7-mc68hc05p9a MOTOROLA For More Information On This Product, R/W Bit Read: Bit 7 6 ...
Page 120
... ADRC bit to logic 1 in the ADC status and control register. Interrupts The ADC cannot generate interrupt requests. 120 For More Information On This Product, converts to digital $FF; an input RH converts to $FF with no overflow. An analog RH converts to digital $00. For ratiometric ADC Go to: www.freescale.com as the RH 8-mc68hc05p9a MOTOROLA ...
Page 121
... AD 4. Source impedances more than 10 k adversely affect internal RC charging time during input sampling External system error caused by input leakage approximately equals R source times input current. 9-mc68hc05p9a MOTOROLA For More Information On This Product, Table 25. ADC Characteristics (V Characteristic (2) > ...
Page 122
... For More Information On This Product, ADC status and control register (ADSCR) ADC data register (ADDR) Bit CCF 0 ADRC ADON Unimplemented Figure 68. ADC Status and Control Register (ADSCR) ADC Go to: www.freescale.com Bit 0 0 CH2 CH1 CH0 10-mc68hc05p9a MOTOROLA ...
Page 123
... This read/write bit turns on the ADC. When the ADC is on, it requires a time, t results can be inaccurate. Resets clear the ADON bit. Bits 4 and 3 — Not used Bits 4 and 3 always read as logic 0s. 11-mc68hc05p9a MOTOROLA For More Information On This Product Internal RC oscillator drives ADC ...
Page 124
... V 101 5 110 6 V 111 7 NOTE: 1. The accuracy of these measurements are untested and not guaranteed. ADC Go to: www.freescale.com Signal AN0 AN1 AN2 AN3 (see Note (see Note 1) (see Note 1) SS Reserved 12-mc68hc05p9a MOTOROLA ...
Page 125
... The STOP instruction turns off the ADC and aborts any current and pending conversions. Wait Mode The ADC continues to operate normally after the WAIT instruction. To reduce power consumption in wait mode: • • 13-mc68hc05p9a MOTOROLA For More Information On This Product, Bit ...
Page 126
... Freescale Semiconductor, Inc. ADC 126 For More Information On This Product, ADC Go to: www.freescale.com 14-mc68hc05p9a MOTOROLA ...
Page 127
... Maximum Supply Current vs. Internal Clock Frequency . . . . . . . . . .136 5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Test Load .139 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 28-Pin PDIP — Case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 28-Pin SOIC — Case #751F . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 5-mc68hc05p9a MOTOROLA For More Information On This Product, Specifications Go to: www.freescale.com Specifications 127 ...
Page 128
... P, MDW (Automotive) Specifications Go to: www.freescale.com within the range Value Unit –0 – 16.75 –65 to +150 on page 130 and on page 132 for guaranteed Symbol Value Unit – –40 to +105 –40 to +125 6-mc68hc05p9a MOTOROLA ...
Page 129
... For most applications, P Ignoring P Solving equations (1) and (2) for K gives: where constant pertaining to the particular part. K can be determined from equation (3) by measuring P known T by solving equations (1) and (2) iteratively for any value of T 7-mc68hc05p9a MOTOROLA For More Information On This Product, Table 29. Thermal Characteristics Characteristic T = ...
Page 130
... Max Unit — — 0.1 V – 0.1 — — – 0.8 — — V — — 0 — — 0 — 4.0 7.0 mA — 2.0 4.0 mA — 1.3 2.0 mA — — — — — 100 A — — — — — — 8-mc68hc05p9a MOTOROLA ...
Page 131
... IH DD linearly by the OSC2 capacitance. 5. Stop mode I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port –0 Input pullup current measured with V 9-mc68hc05p9a MOTOROLA For More Information On This Product, = 5.0 Vdc) DD Symbol I INPU C OUT – +85 C, unless otherwise noted. ...
Page 132
... PD5 RH I — IN Specifications Go to: www.freescale.com (1) (2) Typ Max Unit — 0.1 V – 0.1 — — – 0.3 — — V — 0 — — 0 — — V 1.3 2.5 mA 1.0 1.4 mA 0.6 1 — — — — 10-mc68hc05p9a MOTOROLA ...
Page 133
... the OSC2 capacitance. 5. Stop mode I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port –0 Input pullup current measured with V 11-mc68hc05p9a MOTOROLA For More Information On This Product, = 3.3 Vdc) DD Symbol I INPU C OUT – +85 C, unless otherwise noted A – ...
Page 134
... For More Information On This Product, 0.8 0.7 0.6 0.5 0.4 (NOTE 3) 0.3 0.2 0.1 0 –3.0 –4.0 –5.0 0 800 –0.8 mA 300 –0.2 mA 0.40 0.35 0.30 (NOTE 3) 0.25 0.20 0.15 0.10 0.05 0 6.0 8.0 10.0 0 400 1.6 mA 300 0.4 mA Specifications Go to: www.freescale.com –1.0 –2.0 –3.0 –4.0 –5.0 I (mA 3 2.0 4.0 6.0 8.0 10.0 I (mA) OL 12-mc68hc05p9a MOTOROLA ...
Page 135
... Freescale Semiconductor, Inc. Typical Supply Current vs. Internal Clock Frequency 2.0 1.5 1.0 0.5 0 0.5 1.0 0 INTERNAL CLOCK FREQUENCY (MHz) Figure 72. Typical Supply Current vs. Internal Clock Frequency 13-mc68hc05p9a MOTOROLA For More Information On This Product, Typical Supply Current vs. Internal Clock Frequency 5.0 RUN MODE 25 C 5.5 V 4.0 4.5 V 3.6 V 3.0 3.0 V 2.0 1.0 0 0.5 1.0 1.5 0 INTERNAL CLOCK FREQUENCY (MHz) 1 ...
Page 136
... INTERNAL CLOCK FREQUENCY (MHz) Figure 73. Maximum Supply Current vs. Internal Clock Frequency 136 For More Information On This Product, 2 3.3 V 10% DD –40 to +125 C Run Mode 2.0 Wait Mode (ADC On) Wait Mode (ADC Off) 1.5 1.0 0.5 0 1.5 2.0 0.5 0 INTERNAL CLOCK FREQUENCY (MHz) Specifications Go to: www.freescale.com 1.0 1.5 2.0 14-mc68hc05p9a MOTOROLA ...
Page 137
... OSC1 Pulse Width RC Oscillator Stabilization Time ADC On Current Stabilization Time 2-bit prescaler in the timer is the limiting factor as it counts The minimum t plus The minimum t plus 19 t 15-mc68hc05p9a MOTOROLA For More Information On This Product, Table 32. Control Timing (V Characteristic 2) OSC ( ...
Page 138
... CYC t — 100 ms OXOV t — 100 ms ILCH t 1.5 — CYC t 4.0 — t RESL CYC 250 — (3) t Note — t TLTL CYC t 250 — ns ILIH (4) t Note — t ILIL CYC 200 — unless otherwise noted H CYC 16-mc68hc05p9a MOTOROLA ...
Page 139
... Freescale Semiconductor, Inc. Test Load TEST POINT Mechanical Specifications The MC68HC05P9A is available in the following packages: • • The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, contact one of the following: • ...
Page 140
... TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 17.80 18.05 0.701 0.711 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 0.035 F 0.41 0.90 0.016 F G 1.27 BSC 0.050 BSC J 0.23 0.32 0.009 0.013 K 0.13 0.29 0.005 0.011 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 18-mc68hc05p9a MOTOROLA ...
Page 141
... Freescale Semiconductor, Inc. accumulator ( 34, ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, ADC (analog-to-digital converter) block diagram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC data register (ADDR) ADC status and control register (ADSCR 120, addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 142
... Freescale Semiconductor, Inc. Index C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . case outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, CCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, central processor unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ceramic resonator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH[2:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . computer operating properly watchdog . . . . . . . . . . . . . . . . . . . . . . condition code register (CCR 30, 39, 53, 55–56, COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 143
... Freescale Semiconductor, Inc. crystal AT-cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . strip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tuning fork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . data direction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, data direction register A (DDRA 18, data direction register B (DDRB 18, data direction register C (DDRC 18, data direction register D (DDRD 18, DCOL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 144
... Freescale Semiconductor, Inc. Index halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . halt instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 55–56, I/O bits ADON bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, ADRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 123, AN[3:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 145
... Freescale Semiconductor, Inc. I/O pins IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, IRQ/V OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PB5/SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, PB6/SDI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, PB7/SCK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, PC3/AN0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 146
... MC68HC05P9A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, IRQ/V 146 For More Information On This Product ...
Page 147
... Freescale Semiconductor, Inc. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . literature updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC in stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . COP in stop, halt, and wait modes . . . . . . . . . . . . . . . . . . . . . . . HALT instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 148
... Freescale Semiconductor, Inc. Index noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, OCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94, 97, OCIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, OLVL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stabilization delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 82, opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 149
... Freescale Semiconductor, Inc. PC6/AN0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, PC7/V PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD7/TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 89, pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 150
... Freescale Semiconductor, Inc. Index RAM locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . registers ADC I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . parallel I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . SIOP I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 151
... Freescale Semiconductor, Inc. SIOP (serial input/output port) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SIOP control register (SCR 107, 112, SIOP data register (SDR ...
Page 152
... Freescale Semiconductor, Inc. Index TCMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 89–90, 96, thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 153
... Freescale Semiconductor, Inc. This document contains the latest data available at publication time. For updates, contact one of the following: Literature Distribution Centers Call or order literature by mail. USA/Europe: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 Phone 1-800-441-2447 or 303-675-2140 Japan: Nippon Motorola Ltd. SPD ...
Page 154
... Freescale Semiconductor, Inc. Literature Updates Mfax Call to access this worldwide faxing service. Or, on the http://Design-NET.com home page, select the Mfax icon. Obtain a fax of complete, easy-to-use Mfax instructions by entering your FAX number and then pressing the 1 key. Motorola SPS World Marketing World Wide Web Server Use the Internet to access this World Wide Web Server ...
Page 155
... What are your recommendations for making this data book more useful? 4. What additional information would you like to see included in future data books? For More Information On This Product, Table of contents Page size/binding Overall impression Go to: www.freescale.com MC68HC05P9A Rev. 3 Technical Data Book High Low Tables ...
Page 156
... Freescale Semiconductor, Inc. CSIC Microcontroller Division Second: fold back along this line Please supply the following information (optional). Name: __________________________________________________________________ Company Name: ________________________________________________________ Title: ____________________________________________________________________ Address:_________________________________________________________________ City: ____________________________________________State: _____Zip:__________ Phone Number: _________________________________________________________ For More Information On This Product, Motorola 6501 William Cannon Drive West ...
Page 157
... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
Page 158
... JAPAN: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 For More Information On This Product, Go to: www.freescale.com Mfax is a trademark of Motorola, Inc. © Motorola, Inc., 1997 MC68HC05P9A/D ...