mc68hc05p4a Freescale Semiconductor, Inc, mc68hc05p4a Datasheet
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... MC68HC05P4A Data Sheet M68HC05 Microcontrollers MC68HC05P4A Rev. 7.1 9/2005 freescale.com ...
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... Corrected World Wide Web address and qualification status 2002 September, 7.1 Updated to meet Freescale identity guidelines. 2005 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor Revision History Description MC68HC05P4A Data Sheet, Rev. 7.1 Page Number(s) N/A Throughout 3 ...
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... MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Chapter 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chapter 5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Chapter 7 Simple Serial Input/Output Port (SIOP Chapter 8 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 9 Computer Operating Properly (COP Chapter 10 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Chapter 11 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 12 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Chapter 13 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 14 Ordering Information Freescale Semiconductor MC68HC05P4A Data Sheet, Rev. 7.1 5 ...
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... List of Chapters 6 MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Condition Code Register (CCR 3.4.1 H — Half Carry 3.4.2 I — Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.3 N — Negative 3.4.4 Z — Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.5 C — Carry/Borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 Stack Pointer (SP 3.6 Program Counter (PC Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Map Chapter 3 Central Processor Unit (CPU) MC68HC05P4A Data Sheet, Rev. 7.1 7 ...
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... SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.2 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 Output Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.4 Input Capture Register 8.5 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.6 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.7 Timer During Wait or Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.8 Timer During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 Chapter 4 Interrupts Chapter 5 Resets Chapter 6 Low-Power Modes Chapter 7 Chapter 8 Timer MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.5 5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.6 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.7 5.0-Volt SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.8 3.3-Volt SIOP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.9 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Freescale Semiconductor Chapter 9 Computer Operating Properly (COP) Chapter 10 Self-Check Mode Chapter 11 Instruction Set Chapter 12 Electrical Specifications MC68HC05P4A Data Sheet, Rev. 7.1 Table of Contents 9 ...
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... Plastic Dual In-Line Package (Case 710-02 13.3 28-Pin Small Outline Integrated Circuit Package (Case 751F-04 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.2 MCU Ordering Forms 14.3 Application Program Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.4 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5 ROM Verification Units (RVUs Chapter 13 Mechanical Specifications Chapter 14 Ordering Information MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... General Description 1.1 Introduction The MC68HC05P4A is a 28-pin MCU (microcontroller unit) based on the MC68HC05P4. The memory map includes 4160 bytes of user ROM and 176 bytes of RAM. The MCU has two 8-bit input/output (I/O) ports, A and C. Port B has three I/O pins and port D has two pins, one that is I/O and the other input only. ...
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... General Description 1.3 Mask Options The MC68HC05P4A has 13 mask options: • CLOCK crystal • IRQ, edge-sensitive only or edge- and level-sensitive • SIOP, most significant bit (MSB) or least significant bit (LSB) first • COP watchdog timer, enable/disable • Keyscan pullups and interrupts on port A, enable/disable by pin • ...
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... POINTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW 176 X 8 4160 X 8 RAM USER ROM 240 X 8 SELF-CHECK ROM Figure 1-1. Block Diagram MC68HC05P4A Data Sheet, Rev. 7.1 MCU Structure COP SYSTEM RESET IRQ PC0 PC1 DATA PORT CPU PC2 DIR REG C REG PC3 ...
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... General Description 1.5 Pin Assignments The MC68HC05P4A pin assignments are shown in RESET PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SDO/PB5 SDI/PB6 SCK/PB7 V 1.6 Signal Description The following paragraphs provide a description of the signals. 1.6.1 V and Power is supplied to the microcontroller through V 1.6.2 IRQ This pin has a mask option that provides two different choices of interrupt triggering sensitivity. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity ...
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... See Freescale Semiconductor V DD MASK OPTION IRQ DDR BIT NORMAL PORT CIRCUITRY Figure 1-3. Port A Pullup Option for a detailed description of the SIOP. The address of the port B Chapter 12 Electrical Specifications. MC68HC05P4A Data Sheet, Rev. 7.1 Signal Description SCHMITT TRIGGER TO INTERRUPT LOGIC Chapter 7 15 ...
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... The I/O pin output mode. The output data latch is read internal signal. DATA DIRECTION REGISTER BIT LATCHED OUTPUT 16 Figure 1-4. Table 1-1. I/O Pin Functions I/O Pin Function DATA BIT INPUT REG BIT INPUT I/O Figure 1-4. I/O Circuitry MC68HC05P4A Data Sheet, Rev. 7.1 I/O OUTPUT PIN Freescale Semiconductor ...
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... Chapter 2 Memory Map 2.1 Introduction The MC68HC05P4A has an 8-Kbyte memory map, consisting of user read-only memory (ROM), user random-access memory (RAM), self-check ROM, and input/output (I/O). See Freescale Semiconductor $0000 I/O 32 Bytes $0020 User ROM (Page Zero) 48 Bytes $0050 RAM 176 Bytes Stack ↑ 64 Bytes ...
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... SIOP Control Register $000A (SCR) SIOP Status Register $000B (SSR) SIOP Data Register $000C (SDR) $000D Unimplemented $000E Unimplemented $000F Unimplemented Figure 2-2. I/O Registers for the MC68HC05P4A (Sheet Bit Read: PA7 PA6 PA5 Write: Reset: Read: PB7 PB6 PB5 ...
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... Dual Timer MSB (DTMH) $001A Counter Alternate Register Dual Timer LSB (DTML) $001B Counter Alternate Register $001C Unimplemented $001D Unimplemented $001E Unimplemented $001F Reserved Figure 2-2. I/O Registers for the MC68HC05P4A (Sheet Freescale Semiconductor Bit Read: ICIE OCIE TOIE Write: Reset ...
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... ROM Security Feature (1) A security feature has been incorporated into the MC68HC05P4A to help prevent external reading of code in the ROM. Placing unique customer code at ROM locations $0028–$002F aids in keeping customer developed software proprietary. 2.4 RAM The user RAM consists of 176 bytes of a shared stack area. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM in the range $00FF to $00C0 ...
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... N — Negative When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Freescale Semiconductor CCR MC68HC05P4A Data Sheet, Rev. 7.1 21 ...
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... The program counter is a 13-bit register that contains the address of the next byte to be fetched. 12 The HC05 CPU core is capable of addressing a 64-Kbyte memory map. For this implementation, however, the addressing registers are limited to an 8-Kbyte memory map NOTE MC68HC05P4A Data Sheet, Rev. 7 Freescale Semiconductor ...
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... IRQ Timer input capture TIMER Timer output capture TIMER Timer overflow TIMER Figure 4-1 MC68HC05P4A Data Sheet, Rev. 7.1 Vector Address $1FFE–$1FFF $1FFC–$1FFD $1FFA–$1FFB $1FF8–$1FF9 $1FF8–$1FF9 $1FF8–$1FF9 and for STOP and WAIT in ...
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... FROM IS I BIT SET N IRQ CLEAR IRQ Y REQUEST LATCH NEXT MC68HC05P4A Data Sheet, Rev. 7.1 STACK PC SET I BIT LOAD PC FROM: IRQ: $1FFA–$1FFB TIMER: $1FF8–$1FF9 COMPLETE INTERRUPT ROUTINE AND EXECUTE RTI Freescale Semiconductor ...
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... IRQ pin must return to the high state before the RTI instruction in the interrupt service routine is executed to avoid the processor re-entering the IRQ service routine. Freescale Semiconductor V DD IRQ LATCH R Figure 4-2. IRQ Function Block Diagram NOTE MC68HC05P4A Data Sheet, Rev. 7.1 Timer Interrupt 6.3 Figure 4-2. TO BIH & BIL INSTRUCTION SENSING TO IRQ PROCESSING IN CPU ...
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... I bit in the CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. 26 NOTE MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... COP timeout was generated. The COP reset function is enabled or disabled by a mask option. Refer to Chapter 9 Computer Operating Properly (COP) Freescale Semiconductor ) oscillator stabilization delay after the oscillator cyc for more information on the COP. MC68HC05P4A Data Sheet, Rev. 7.1 27 ...
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... The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. Internal Address 1FFE 1FFF 1 Bus Internal New New Data PCH PCL 1 Bus RESET 28 New 1FFE PC Op Code Figure 5-1. Power-On Reset and RESET MC68HC05P4A Data Sheet, Rev. 7.1 New 1FFE 1FFE 1FFE 1FFF PC Op PCH PCL PCH PCL Code Freescale Semiconductor ...
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... Low-Power Modes 6.1 Introduction The MC68HC05P4A is capable of running in a low-power mode in each of its configurations. The WAIT and STOP instructions provide two modes that reduce the power required for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the computer operating properly (COP) watchdog timer is enabled ...
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... DELAY? RESTART INTERNAL PROCESSOR CLOCK 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT a. STACK b. SET I BIT c. VECTOR TO INTERRUPT ROUTINE Figure 6-1. STOP/WAIT Flowchart MC68HC05P4A Data Sheet, Rev. 7.1 WAIT EXTERNAL OSCILLATOR ACTIVE AND INTERNAL TIMER CLOCK ACTIVE STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR EXTERNAL ...
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... In master mode, the format is identical except that the SCK pin is an output and the shift clock now originates internally. The master mode transmission frequency is fixed at E/4. Freescale Semiconductor RESET 8-BIT SHIFT REGISTER MSB/LSB MASK OPTION DATA BUS Figure 7-1. SIOP Block Diagram MC68HC05P4A Data Sheet, Rev. 7.1 SDO SCK SDI 31 ...
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... B to its normal I/O function. Reset clears this bit. 32 BIT 1 BIT 2 BIT 3 BIT 1 BIT 2 BIT 3 Figure 7-2. Serial I/O Port Timing SPE MSTR Figure 7-3. SIOP Control Register (SCR) MC68HC05P4A Data Sheet, Rev. 7.1 BIT 7 BIT 8 BIT 7 BIT Bit Freescale Semiconductor ...
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... If the DCOL bit is set and the SPIF is not set, clearing the DCOL requires turning the SIOP off then turning it back on. Reset also clears this bit. Freescale Semiconductor DCOL Figure 7-4. SIOP Status Register (SSR) NOTE MC68HC05P4A Data Sheet, Rev. 7.1 SIOP Registers 2 1 Bit ...
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... SIOP is enabled (SPE = 1). Address: $000C Bit 7 Read: BIT 7 Write: Reset BIT 6 BIT 5 BIT 4 BIT 3 Unaffected by reset Figure 7-5. SIOP Data Register (SDR) MC68HC05P4A Data Sheet, Rev. 7 Bit 0 BIT 2 BIT 1 BIT 0 Freescale Semiconductor ...
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... COUNTER COUNTER $1A ALTERNATE $1B REGISTER EDGE OVERFLOW DETECT DETECT CIRCUIT CIRCUIT OUTPUT LEVEL $13 REG. TIMER CONTROL ICIE OCIE TOIE IEDG OLVL REG. $12 Figure 8-1. Timer Block Diagram MC68HC05P4A Data Sheet, Rev. 7.1 LOW BYTE $14 $ CLK C RESET EDGE OUTPUT INPUT LEVEL (TCAP) (TCMP) 35 ...
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... After a processor write cycle to the output compare register containing the MSB ($16), the output compare function is inhibited until the LSB ($17) is also written. The user must write both bytes (locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare function. The 36 NOTE MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... ICIE — Input Capture Interrupt Enable Bit 1 = Interrupt enabled 0 = Interrupt disabled OCIE — Output Compare Interrupt Enable Bit 1 = Interrupt enabled 0 = Interrupt disabled Freescale Semiconductor OCIE TOIE MC68HC05P4A Data Sheet, Rev. 7.1 Input Capture Register 2 1 Bit 0 0 IEDG OLVL ...
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... Accessing the timer status register satisfies the first condition required to clear status bits. The remaining step is to access the register corresponding to the status bit OCF TOF Figure 8-3. Timer Status Register (TSR) MC68HC05P4A Data Sheet, Rev. 7 Bit Freescale Semiconductor ...
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... MCU, but when the MCU does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. If RESET is used to exit stop mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Freescale Semiconductor MC68HC05P4A Data Sheet, Rev. 7.1 Timer During Wait or Halt Mode 39 ...
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... Timer 40 MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Halt mode is not intended for normal use. This feature is provided to keep the COP watchdog timer active in the event a STOP instruction is inadvertently executed. Freescale Semiconductor NOTE MC68HC05P4A Data Sheet, Rev. 7.1 41 ...
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... Computer Operating Properly (COP) 42 MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Freescale Semiconductor Table Table 10-1. Self-Check Results PC1 PC0 0 1 Bad I Bad RAM 1 1 Bad timer 0 0 Bad ROM 0 1 Bad serial 1 0 Bad interrupt Flashing Good device All others Bad device MC68HC05P4A Data Sheet, Rev. 7.1 10- not recommended that the Remarks 43 ...
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... PA2 8 21 PA1 9 20 PA0 10 19 SDO/PB5 11 18 SDI/PB6 12 17 SCK/PB7 Figure 10-1. Self-Check Circuit MC68HC05P4A Data Sheet, Rev. 7 Ω OSC1 4 MHz OSC2 TCAP/PD7 TCMP Ω PD5 PC0 PC1 PC2 PC3 PC4 PC5 ...
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... In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are 3-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. Freescale Semiconductor MC68HC05P4A Data Sheet, Rev. 7.1 45 ...
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... When using the Freescale assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 46 MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Subtract memory byte and carry bit from accumulator Store accumulator in memory Store index register in memory Subtract memory byte from accumulator Freescale Semiconductor Table 11-1 lists the register/memory instructions. Instruction MC68HC05P4A Data Sheet, Rev. 7.1 Instruction Types Mnemonic ADC ADD AND BIT CMP CPX ...
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... Decrement Increment Logical shift left Logical shift right Negate (two’s complement) Rotate left through carry bit Rotate right through carry bit Test for negative or zero 48 Instruction MC68HC05P4A Data Sheet, Rev. 7.1 Table 11-2 Mnemonic ASL ASR BCLR BSET CLR COM DEC INC ...
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... Branch if not equal Branch if plus Branch always Branch if bit clear Branch never Branch if bit set Branch to subroutine Unconditional jump Jump to subroutine Freescale Semiconductor Instruction Mnemonic MC68HC05P4A Data Sheet, Rev. 7.1 Instruction Types BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO ...
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... Stop oscillator and enable IRQ pin software interrupt Transfer accumulator to index register Transfer index register to accumulator Stop CPU clock and enable interrupts 50 Table 11-4 lists these instructions. Instruction Table 11-5. Control Instructions Instruction MC68HC05P4A Data Sheet, Rev. 7.1 Mnemonic BCLR BRCLR BRSET BSET Mnemonic CLC CLI NOP RSP ...
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... PC ← (PC rel ? ← (PC rel ? ← (PC rel ? ← (PC rel ? ← (PC rel ? C ∨ — — — — — PC ← (PC rel ? MC68HC05P4A Data Sheet, Rev. 7.1 Instruction Set Summary Effect on CCR ...
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... PC ← (PC rel ? ← (PC rel ? ← ← (PC push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – ← (PC) + rel C ← ← 0 MC68HC05P4A Data Sheet, Rev. 7.1 Effect on CCR — — — — — REL — ...
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... A ← ( ← ( ← ( ← ( ← Jump Address PC ← (PC Push (PCL); SP ← (SP) – 1 Push (PCH); SP ← (SP) – ← Effective Address MC68HC05P4A Data Sheet, Rev. 7.1 Instruction Set Summary Effect on CCR DIR 3F 5 INH ...
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... M ← –(M) = $00 – (M) A ← –(A) = $00 – (A) X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) A ← (A) ∨ ( ← $00FF MC68HC05P4A Data Sheet, Rev. 7.1 Effect on CCR IMM A6 DIR EXT C6 — ...
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... SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte X ← (A) (M) – $00 MC68HC05P4A Data Sheet, Rev. 7.1 Instruction Set Summary Effect on CCR INH 80 9 — ...
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... ∧ ∨ ⊕ –( ) ← — MC68HC05P4A Data Sheet, Rev. 7.1 Effect on CCR — — — — — INH 9F — 0 — — — INH 8F Operand (one or two bytes) Program counter Program counter high byte Program counter low byte ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 ...
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... Instruction Set 58 MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... Characteristic Operating temperature range MC68HC05P4AP (standard) MC68HC05P4ACP (extended) 12.4 Thermal Characteristics Characteristic Thermal resistance Plastic DIP Plastic SOIC Freescale Semiconductor and V SS NOTE for guaranteed operating conditions. MC68HC05P4A Data Sheet, Rev. 7.1 and V within the range In Out Symbol Value V –0 7 –0.3 to ...
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... Out –40 °C to +85 °C, unless otherwise noted –0 MC68HC05P4A Data Sheet, Rev. 7.1 Min Typ Max — — 0.1 V –0.1 — — –0.8 — — –0.8 — — DD — ...
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... Out –40 °C to +85 °C, unless otherwise noted MC68HC05P4A Data Sheet, Rev. 7.1 3.3-Volt DC Electrical Characteristics Min Typ Max — — 0.1 V –0.1 — — –0.3 — — –0.3 — — ...
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... SDI setup time 6 SDI hold time Notes: = 3.3 Vdc ± 10 Vdc 1.0 MHz maximum –40 °C to +85 °C, unless otherwise noted A = –40 °C to +85 °C, unless otherwise noted A MC68HC05P4A Data Sheet, Rev. 7.1 Symbol Min Max f 0.25 0.25 op( 0.25 op(s) t 4.0 4.0 cyc(m) t — ...
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... Figure 12-1. SIOP Timing Diagram Symbol f osc cyc t OXOV t ILCH ILIH t ILIL t OH, = –40 °C to +85 °C, unless otherwise noted A MC68HC05P4A Data Sheet, Rev. 7.1 5.0-Volt Control Timing BIT 7 6 BIT 7 5 Min Max Unit — 4.2 MHz dc 4.2 — 2.1 MHz dc 2.1 480 — ns — ...
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... OXOV t ILCH ILIH t ILIL t OH, = –40°C to +85°C, unless otherwise noted A t 4064 cyc 1FFE 1FFE Figure 12-2. STOP Recovery Timing MC68HC05P4A Data Sheet, Rev. 7.1 Min Max Unit — 2.0 MHz dc 2.0 — 1.0 MHz dc 1.0 1000 — ns — 100 ms — 100 ...
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... Figure 12-3. External Interrupt Timing t 4064 cyc 1FFE 1FFE 1FFE rises through a threshold (typically 1–2 V). DD Figure 12-4. Power-On Reset Timing MC68HC05P4A Data Sheet, Rev. 7.1 3.3-Volt Control Timing Edge-Sensitive Trigger Condition The minimum pulse width ( either ILIH 125 250 V). DD ...
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... The next rising edge of the internal processor clock after the rising edge of RESET initiates the reset sequence. 66 1FFE 1FFE 1FFE 1FFE NEW PCH t RL Figure 12-5. External Reset Timing MC68HC05P4A Data Sheet, Rev. 7.1 1FFF NEW PC NEW PC NEW OP DUMMY PCL CODE Freescale Semiconductor ...
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... SEATING PLANE MC68HC05P4A Data Sheet, Rev. 7.1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS ...
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... 45° C -T- SEATING PLANE K J MC68HC05P4A Data Sheet, Rev. 7.1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0 ...
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... Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. Freescale Semiconductor ( 1/2-inch diskette (double-sided 720 K or double-sided high-density 5 1/4-inch diskette (double-sided double- density 360 K or double-sided MC68HC05P4A Data Sheet, Rev. 7.1 14.3 Application Program Media 69 ...
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... ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Freescale Quality Assurance. 70 NOTE MC68HC05P4A Data Sheet, Rev. 7.1 Freescale Semiconductor ...
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... P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC68HC05P4A Rev. 7.1, 9/2005 RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. ...