mc68hc05j5ap Freescale Semiconductor, Inc, mc68hc05j5ap Datasheet
mc68hc05j5ap
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... Freescale Semiconductor, Inc. 68HC05J5A 68HRC05J5A 68HC705J5A 68HRC705J5A SPECIFICATION (General Release) July 16, 1999 Semiconductor Products Sector For More Information On This Product, Go to: www.freescale.com HC05J5AGRS/H REV 2.1 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Section 1.1 FEATURES ...................................................................................................... 1-1 1.2 MASK OPTIONS.............................................................................................. 1-2 1.3 MCU STRUCTURE.......................................................................................... 1-2 1.4 PIN ASSIGNMENTS ........................................................................................ 1-4 1.5 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4 1.5.1 V AND V .............................................................................................. 1 1.5.2 OSC1, OSC2/R............................................................................................ 1-4 1.5.3 RESET......................................................................................................... 1-6 1.5.4 IRQ (MASKABLE INTERRUPT REQUEST)................................................ 1-6 1.5.5 PA0-PA7 ...................................................................................................... 1-6 1.5.6 PB0-PB5 ...................................................................................................... 1-7 2.1 I/O AND CONTROL REGISTERS ................................................................... 2-2 2.2 RAM ................................................................................................................. 2-2 2.3 ROM................................................................................................................. 2-2 2.4 I/O REGISTERS SUMMARY ........................................................................... 2-3 CENTRAL PROCESSING UNIT 3.1 REGISTERS .................................................................................................... 3-1 3.2 ACCUMULATOR (A)........................................................................................ 3-2 3.3 INDEX REGISTER (X) ..................................................................................... 3-2 3.4 STACK POINTER (SP) .................................................................................... 3-2 3 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section 4.5.2 OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) .................................... 4-6 4.5.3 TIMER INTERRUPT (MFT) ......................................................................... 4-7 4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)........................................................ 4-7 5.1 EXTERNAL RESET (RESET).......................................................................... 5-2 5.2 INTERNAL RESETS ........................................................................................ 5-2 5.2.1 POWER-ON RESET (POR) ........................................................................ 5-2 5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)........................... 5-2 5.2.3 LOW VOLTAGE RESET (LVR) ................................................................... 5-3 5.2.4 ILLEGAL ADDRESS RESET (ILADR)......................................................... 5-3 6.1 STOP INSTRUCTION...................................................................................... 6-2 6 ...
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... Freescale Semiconductor, Inc. Section 8.1 OVERVIEW...................................................................................................... 8-2 8.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2 8.3 MFT REGISTERS ............................................................................................ 8-2 8.3.1 Timer Counter Register (TCR) $09.............................................................. 8-3 8.3.2 Timer Control/Status Register (TCSR) $08 ................................................. 8-3 8.4 OPERATION DURING STOP MODE .............................................................. 8-5 8.5 OPERATION DURING WAIT/HALT MODE..................................................... 8-5 9.1 TIMER1 COUNTER REGISTERS (TCNTH, TCNTL) ...................................... 9-2 9.2 ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL).............................. 9-3 9.3 INPUT CAPTURE REGISTERS ...................................................................... 9-5 9 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Section ELECTRICAL SPECIFICATIONS 11.1 MAXIMUM RATINGS..................................................................................... 11-1 11.2 THERMAL CHARACTERISTICS ................................................................... 11-1 11.3 FUNCTIONAL OPERATING RANGE ............................................................ 11-1 11.4 DC ELECTRICAL CHARACTERISTICS........................................................ 11-2 11.5 CONTROL TIMING ........................................................................................ 11-5 MECHANICAL SPECIFICATIONS 12.1 16-PIN PDIP (CASE #648) ............................................................................ 12-1 12.2 16-PIN SOIC (CASE #751G) ......................................................................... 12-1 12.3 20-PIN PDIP (CASE #738) ............................................................................ 12-2 12.4 20-PIN SOIC (CASE #751D) ......................................................................... 12-2 A.1 INTRODUCTION..............................................................................................A-1 A.2 RC OSCILLATOR CONNECTIONS.................................................................A-1 A ...
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... Freescale Semiconductor, Inc. Figure 1-1 MC68HC05J5A Block Diagram........................................................................ 1-3 1-2 Pin Assignments for 16-Pin and 20-Pin Packages........................................... 1-4 1-3 Oscillator Connections ..................................................................................... 1-5 2-1 MC68HC05J5A Memory Map .......................................................................... 2-1 2-2 I/O Registers Memory Map .............................................................................. 2-2 2-3 I/O Registers $0000-$000F.............................................................................. 2-3 2-4 I/O Registers $0010-$001F.............................................................................. 2-4 3-1 MC68HC05 Programming Model ..................................................................... 3-1 4-1 Interrupt Processing Flowchart ........................................................................ 4-2 4-2 IRQ Function Block Diagram............................................................................ 4-3 4-3 IRQ Status & Control Register ......................................................................... 4-5 5-1 Reset Block Diagram ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Figure vi For More Information On This Product, July 16, 1999 LIST OF FIGURES Title Go to: www.freescale.com Page MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. Table 4-1 Vector Address for Interrupts and Reset.......................................................... 4-1 6-1 COP Watchdog Timer Recommendations ....................................................... 6-5 7-1 Port A I/O Pin Functions................................................................................... 7-7 7-2 Port B I/O Pin Functions................................................................................... 7-7 8-1 RTI Rates and COP Reset Times .................................................................... 8-5 10-1 Register/Memory Instructions ........................................................................ 10-4 10-2 Read-Modify-Write Instructions ..................................................................... 10-5 10-3 Jump and Branch Instructions........................................................................ 10-6 10-4 Bit Manipulation Instructions .......................................................................... 10-7 10-5 Control Instructions ........................................................................................ 10-7 10-6 Instruction Set Summary ............................................................................... 10-8 10-7 Opcode Map ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table viii For More Information On This Product, July 16, 1999 LIST OF TABLES Title Go to: www.freescale.com Page MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. GENERAL DESCRIPTION The MC68HC05J5A is a member of the low-cost high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION • 14 Bidirectional I/O pins (10 I/O pins on 16-pin package) – PA0-PA5, PB0, and PB3-PB5: with software programmable input pull- down devices – PB1, PB2, PA6 and PA7: open-drained I/O pins with software programmable pull-up devices – PA6, PA7, and PB1: with slow output falling transition feature – ...
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... Freescale Semiconductor, Inc. PA0 PA1 PA2 PORT DATA PA3 A DIR REG REG PA4 PA5 PA6 PA7 PB0 PB1 PORT DATA PB2 B DIR PB3 REG REG PB4 PB5 : External edge interrupt capability : 8 mA current sink : Open-drained with internal pull-up and 8 mA current sink ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.4 PIN ASSIGNMENTS 1 16 OSC2/R OSC1 RESET PA7 4 13 PA6 5 12 PA5 6 11 PA4 7 10 PB0/TCAP 8 IRQ/VPP: VPP is only available on EPROM parts Figure 1-2. Pin Assignments for 16-Pin and 20-Pin Packages 1.5 FUNCTIONAL PIN DESCRIPTION The following paragraphs give a description of the general function of each pin assigned in Figure 1-2 ...
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... Freescale Semiconductor, Inc crystal as shown in Figure 1-3 ( ceramic resonator as shown in Figure 1-3 ( external clock signal as shown in Figure 1-3 (b) The frequency the oscillator or external clock source is divided by two to OSC produce the internal operating frequency, f Crystal Oscillator The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer’ ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1.5.3 RESET This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to V internal pull-up is also connected between this pin and V tains an internal Schmitt trigger to improve its noise immunity as an input ...
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... Freescale Semiconductor, Inc. can be enabled or disabled by software. Both PA6 and PA7 pins have Schmitt trigger input for better noise immunity. V respectively. The slow transition feature of PA6 and PA7 pins can be enabled or disabled by software. Once enabled, slow transition feature is applied to both pins while in output mode ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 1-8 For More Information On This Product, July 16, 1999 GENERAL DESCRIPTION Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. The MC68HC05J5A has 4K-bytes of addressable memory consisting 32 bytes of I/O, 128 bytes of user RAM, and 2560 bytes of user ROM, as shown in Figure 2-1. $0000 0000 I/O 32 Bytes $001F 0031 0032 $0020 unimplemented 96 Bytes $007F 0127 0128 $0080 User RAM 128 Bytes $00C0 0192 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 2.1 I/O AND CONTROL REGISTERS The I/O and Control Registers reside in locations $0000-$001F. The overall orga- nization of these registers is shown in Figure 2-2. The bit assignments for each register are shown in Figure 2-3 and Figure 2-4. Reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. ...
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... Freescale Semiconductor, Inc. 2.4 I/O REGISTERS SUMMARY ADDR REGISTER R/W Port A Data R $0000 PORTA W Port B Data R $0001 PORTB W R Timer1 Capture Control $0002 T1CC W R $0003 Unimplemented W Port A Data Direction R $0004 DDRA W Port B Data Direction R $0005 DDRB W R $0006 Unimplemented W R $0007 Unimplemented W MFT Ctrl/Status ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION ADDR REGISTER R/W Port A Pull-down/up R $0010 PDURA W Port B Pull-down/up R $0011 PDURB W Timer1 Control R $0012 T1CR W Timer1 Status R $0013 T1SR W Input Capture High R $0014 ICH W Input Capture Low R $0015 ICL W R $0016 Unimplemented W R $0017 Unimplemented W Timer1 Counter High ...
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... Freescale Semiconductor, Inc. CENTRAL PROCESSING UNIT The MC68HC05J5A has an 4k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.2 ACCUMULATOR (A) The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device. 3.3 INDEX REGISTER (X) The index register shown in Figure 3 8-bit register that can perform two functions: • ...
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... Freescale Semiconductor, Inc. Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 CONDITION CODE REGISTER (CCR) The CCR shown in Figure 3 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 3.6.5 Carry/Borrow Bit (C-Bit) The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates ...
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... Freescale Semiconductor, Inc. The MCU can be interrupted in six different ways: • Non-maskable Software Interrupt Instruction (SWI) • External Asynchronous Interrupt (IRQ) • Optional External Interrupt via IRQ on PA0-PA3 (by a mask option) • External Interrupt via IRQ on PA7 • Multi-Function Timer (MFT) • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occur during interrupt processing ...
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... Freescale Semiconductor, Inc. 4.3 SOFTWARE INTERRUPT (SWI) The SWI is an executable instruction and a non-maskable interrupt since it is exe- cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter- rupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address is specified by the con- tents of memory locations $0FFC and $0FFD ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The IRQ pin is a source of IRQ interrupts and a mask option can also enable the other four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources. The last source of IRQ interrupt comes from PA7 whenever there is a falling edge on PA7 and IRQE1 is enabled ...
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... Freescale Semiconductor, Inc. 4.5.1 IRQ CONTROL/STATUS REGISTER (ICSR) $0A The IRQ interrupt function is controlled by the ICSR located at $000A. All unused bits in the ICSR will read as logic zeros. The IRQF, IRQF1, IRQE1 bits are cleared and IRQE bit is set by reset ICSR IRQE IRQE1 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION IRQF - IRQ Interrupt Request Flag Writing to the IRQF flag bit will have no effect on it. If the additional setting of IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains set the CPU will re-enter the IRQ interrupt sequence continuously until either the IRQF fl ...
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... Freescale Semiconductor, Inc. The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 thru PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 4-8 For More Information On This Product, July 16, 1999 INTERRUPTS Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. The MCU can be reset from five sources: one external input and four internal restart conditions. • Initial power up of device (power on reset) • A logic zero applied to the RESET pin (external reset) • Timeout of the COP watchdog (COP reset) • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5.1 EXTERNAL RESET (RESET) The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage sepa- rated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold ...
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... Freescale Semiconductor, Inc. The COPR will generate the RST signal which will reset the CPU and other peripherals. Also, the COPR will establish the mode of operation based on the state of the IRQ pin at the time the COPR signal ends. If the voltage on the IRQ ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 5-4 For More Information On This Product, July 16, 1999 RESETS Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. There are three modes of operation that reduce power consumption: • Stop mode • Wait mode • Halt mode The WAIT and STOP instructions provide two power saving modes by stopping various internal modules and/or the on-chip oscillator. The STOP and WAIT instructions are not normally used if the COP Watchdog Timer is enabled ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION STOP Stop Y Conversion to Halt? N Stop External Oscillator, Stop Internal Timer Clock, Reset Startup Delay Stop Internal Processor Clock, Clear I-Bit in CCR, and set IRQE in ICSR Y External RESET? N IRQ Y External Interrupt? Restart External Oscillator, N start Stabilization Delay ...
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... Freescale Semiconductor, Inc. STOP Mode. The other option is for the STOP instruction to behave like a WAIT instruction (except that the restart time will involve a delay) and place the device in the HALT Mode. 6.1.1 STOP Mode Execution of the STOP instruction in this mode (selected by a mask option) places the MCU in its lowest power consumption mode ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION after a varied delay time which is from one to 224 or 4064 internal processor clock cycles (the POR delay time). The HALT Mode is not intended for normal use, but is provided to keep the COP Watchdog Timer active should the STOP instruction opcode be inadvertently executed ...
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... Freescale Semiconductor, Inc. The recommended interactions and considerations for the COP Watchdog Timer, STOP instruction, and WAIT instruction are summarized in Table 6-1. Table 6-1. COP Watchdog Timer Recommendations IF the following conditions exist: STOP Instruction converted to HALT by mask option converted to HALT by mask option Acts as STOP REV 2 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6-6 For More Information On This Product, July 16, 1999 LOW POWER MODES Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. In the normal operating mode there are 14 usable bidirectional I/O lines arranged as one 8-bit I/O port (Port A), and one 6-bit I/O port (Port B). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDR’s). Also, if enabled by a single mask option all Port A and Port B I/O pins may have individual software programmable pull-down or pull-up devices ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Each Port A pin is controlled by the corresponding bits in a data direction register, a data register and a pulldown/up register. The Port A Data Register is located at address $0000. The Port A Data Direction Register (DDRA) is located at address $0004. The Port A Pulldown/up Register (PDURA) is located at address $0010. ...
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... Freescale Semiconductor, Inc. 7.2.3 Port A Pulldown/up Register All Port A I/O pins may have software programmable pulldown/up devices enabled by the applicable mask option. If the pulldown/up mask option is selected, the pull- down/up is activated whenever the corresponding bit in the PDURA is clear. If the corresponding bit in the PDURA bit is set or the mask option for pulldown/up is not chosen, the pulldown/up will be disabled ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7.3 PORT B Port 6-bit bidirectional port which functions as shown in Figure 7-3. Only PB1 and PB2 are of open-drained type. Each Port B pin is controlled by the corre- sponding bits in a data direction register, a data register and a pulldown/up regis- ter. The Port B Data Register is located at address $0001. The Port B Data Direction Register (DDRB) is located at address $0005 ...
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... Freescale Semiconductor, Inc. corresponding I/O pin. The Port B data register is unaffected by reset. Unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored. The Port B data register is unaffected by reset. 7.3.2 Port B Data Direction Register Port B I/O pins may be programmed as an input by clearing the corresponding bit in the DDRB, or programmed as an output by setting the corresponding bit in the DDRB ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION I/O pin is activated only if the I/O pin is programmed as an input whereas a pullup device on an I/O pin is always activated whenever enabled, regardless of port direction. The PDURB is a write-only register. Any reads of location $0011 will return unde- fined results. Since reset clears both the DDRB and the PDURB, all pins will ini- tialize as inputs with the pulldown devices active and pullup devices active (if chosen via mask option) ...
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... Freescale Semiconductor, Inc. If the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen) the input pin will also have an activated pulldown/up device. Since the pulldown/up register bits are write-only, bit manipulation should not be used on these register bits. 7.4.4 I/O Pin Transitions A " ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 7-8 For More Information On This Product, July 16, 1999 INPUT/OUTPUT PORTS Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. MULTI-FUNCTION TIMER The Multi-Function Timer module is a 15-stage ripple counter with Timer Over Flow (TOF), Real Time Interrupt (RTI), COP Watchdog, and the Power-On Reset delay function. 8 Timer Counter Register (TCR) 8 TCR ÷2 Overflow RTI Select Circuit ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8.1 OVERVIEW As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by four. NTF1 has the same phase and frequency as the processor bus clock, PH2, but is not stopped by the WAIT or HALT Modes. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter Register (TCR) at address $09. A timer overfl ...
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... Freescale Semiconductor, Inc. 8.3.1 Timer Counter Register (TCR) $09 The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f divided by 4 and can be used for various functions including a soft- op ware input capture ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION RTIF - Real Time Interrupt Flag The RTIF is a read-only flag bit Set when the output of the chosen ( selections) Real Time Interrupt stage goes active. A TIMER Interrupt request will be generated if RTIE is also set Reset by writing a logical one to the RTIF acknowledge bit, RTIFR. ...
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... Freescale Semiconductor, Inc. Table 8-1. RTI Rates and COP Reset Times RTI Rates RT1 RT0 Divider 1MHz 16384 16.384ms 0 0 32768 32.768ms 0 1 65536 65.536ms 1 0 131072 131.072ms 1 1 8.4 OPERATION DURING STOP MODE The timer system is cleared when going into STOP mode. When STOP is exited ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 8-6 For More Information On This Product, July 16, 1999 MULTI-FUNCTION TIMER Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. This 16-bit Timer (Timer1 Programmable Timer with an Input Capture function. Figure 9-1 shows a block diagram of the 16-bit programmable timer. EDGE SIGNAL PB0/ SELECT TCAP CONDITIONING & DETECT LOGIC TCAPS (bit 7 at $02) RESET TIMER1 CONTROL REGISTER $12 INTERNAL DATA BUS Figure 9-1 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION The basis of the 16-bit Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and output ...
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... Freescale Semiconductor, Inc. The timer counter registers (TCNTH, TCNTL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. BIT 7 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION counter will not have any effect on the T1OF flag bit and Timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16- bit timer counter. READ READ ACNTH ($FFFC) RESET Figure 9-4. Alternate Counter Block Diagram ...
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... Freescale Semiconductor, Inc. To prevent interrupts from occurring between readings of the ACNTH and ACNTL, set the I bit in the condition code register (CCR) before reading ACNTH and clear the I bit after reading ACNTL. 9.3 INPUT CAPTURE REGISTERS READ ICH EDGE SIGNAL PB0/ SELECT & DETECT ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION BIT 7 BIT 6 T1CC R TCAPS $0002 W reset: 0 Figure 9-7. Timer1 Capture Control Register TCAPS — Timer Input Capture Comparator Enable 1 = Timer input capture comparator is selected Timer input capture comparator schmitt trigger is selected. When the comparator and V becomes an input pin, irrespective of DDR setting. However recommended to set PB0 as an input fi ...
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... Freescale Semiconductor, Inc ÷ Figure 9-9. TCAP Input Comparator Output When the input capture circuitry detects an active edge on the TCAP pin, it latches the contents of the free-running timer counter registers into the input cap- ture registers as shown in Figure 9-6. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Reading the ICH inhibits further captures until the ICL is also read. Reading the ICL after reading the timer status register (T1SR) clears the ICF flag bit. does not inhibit transfer of the free-running counter. There is no conflict between reading the ICL and transfers from the free-running timer counters ...
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... Freescale Semiconductor, Inc. IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transi- tion on the TCAP pin triggers a transfer of the contents of the timer register to the input capture register. Reset has no effect on the IEDG bit Positive edge (low to high transition) triggers input capture. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION time the counter resumes from its stopped value as if nothing had happened. If STOP mode is exited via an external reset (logic low applied to the RESET pin) the counter is forced to $FFFC valid input capture edge occurs at the PB0/TCAP pin during the STOP mode the input capture detect circuitry will be armed. This action does not set any fl ...
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... Freescale Semiconductor, Inc. This section describes the addressing modes and instruction types. 10.1 ADDRESSING MODES The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: • ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.1.3 Direct Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address ...
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... Freescale Semiconductor, Inc. 10.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.1.10 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 10-1 lists the register/memory instructions. Table 10-1. Register/Memory Instructions Add Memory Byte and Carry Bit to Accumulator ...
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... Freescale Semiconductor, Inc. 10.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST exception to the read-modify-write sequence because it does not write a replacement value. Table 10-2 lists the read-modify-write instructions ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. ...
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... Freescale Semiconductor, Inc. 10.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the fi ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 10.1.15 Instruction Set Summary Table 10 alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 10-6. Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ...
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... Freescale Semiconductor, Inc. Table 10-6. Instruction Set Summary (Continued) Source Operation Form Branch if Half-Carry BHCC rel Bit Clear Branch if Half-Carry BHCS rel Bit Set BHI rel Branch if Higher Branch if Higher or BHS rel Same Branch if IRQ Pin BIH rel High Branch if IRQ Pin ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 10-6. Instruction Set Summary (Continued) Source Operation Form BSET n opr Set Bit n Branch to BSR rel Subroutine CLC Clear Carry Bit CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr ...
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... Freescale Semiconductor, Inc. Table 10-6. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment Byte INC opr ,X INC ,X JMP opr JMP opr JMP opr ,X Unconditional Jump JMP opr ,X JMP ,X JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 10-6. Instruction Set Summary (Continued) Source Operation Form ORA # opr ORA opr Logical OR ORA opr Accumulator with ORA opr ,X Memory ORA opr ,X ORA ,X ROL opr ROLA Rotate Byte Left ROLX through Carry Bit ROL opr ,X ...
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... Freescale Semiconductor, Inc. Table 10-6. Instruction Set Summary (Continued) Source Operation Form SUB # opr SUB opr Subtract Memory SUB opr Byte from SUB opr ,X Accumulator SUB opr ,X SUB ,X SWI Software Interrupt Transfer TAX Accumulator to Index Register TST opr TSTA Test Memory Byte ...
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Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 BCLR0 BRN ...
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... Freescale Semiconductor, Inc. ELECTRICAL SPECIFICATIONS This section provides the electrical and timing specifications for the MC68HC05J5A. 11.1 MAXIMUM RATINGS (Voltages referenced Rating Supply Voltage Test Mode (IRQ Pin Only) Current Drain Per Pin Excluding PB1, PB2, V Operating Junction Temperature Storage Temperature Range Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11.4 DC ELECTRICAL CHARACTERISTICS Table 11-1. DC Electrical Characteristics Characteristic Output Voltage I = 10.0 A Load Output High Voltage (I =–0.8 mA) PA0-5, PB0, PB3-5 Load Output Low Voltage (I = 1.6mA) PA0-3, PB0, PB3-5 Load (I = 8mA) PA4-7 Load (I = 25mA) PB1, PB2 (see note 8) ...
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... Freescale Semiconductor, Inc. Table 11-1. DC Electrical Characteristics Characteristic Pull-up Resistor 6 PA6, PA7 PB1, PB2 LVR Trigger Voltage TCAP Input Threshold Voltage 5.0Vdc ±10 Vdc Typical values reflect average measurements at midpoint of voltage range only. 3. Run (Operating Wait I ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION Table 11-2. DC Electrical Characteristics Characteristic I/O Ports Hi-Z Leakage Current PA0-7, PB0-5 (without individual pull-down/up activated) Input Pull-down Current PA0-5, PB0, PB3-5 (with individual pull-down activated) Input Pull-up Current RESET Input Current IRQ, OSC1 Capacitance Ports (as Input or Output) ...
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... Freescale Semiconductor, Inc. 11.5 CONTROL TIMING Table 11-3. Control Timing Characteristic Frequency of Operation Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (f 2) OSC External Clock (f 2) OSC Cycle Time (1 RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 11-6 For More Information On This Product, July 16, 1999 ELECTRICAL SPECIFICATIONS Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. MECHANICAL SPECIFICATIONS This section provides the mechanical dimensions for the four available packages for MC68HC05J5A. 12.1 16-PIN PDIP (CASE #648) –A– 0.25 (0.010) Figure 12-1. 16-Pin PDIP Mechanical Dimensions 12.2 16-PIN SOIC (CASE #751G) – ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 12.3 20-PIN PDIP (CASE #738) –A– –T– SEATING PLANE 0.25 (0.010) Figure 12-3. 20-Pin PDIP Mechanical Dimensions 12.4 20-PIN SOIC (CASE #751D) –A– –B– 10X 20X 0.010 (0.25 ...
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... Freescale Semiconductor, Inc. This appendix describes the MC68HRC05J5A, a resistor-capacitor (RC) oscillator mask option version of the MC68HC05J5A. The entire MC68HC05J5A data sheet applies to the MC68HRC05J5A, with exceptions outlined in this appendix. A.1 INTRODUCTION The MC68HRC05J5A is a resistor-capacitor (RC) oscillator mask option version of the MC68HC05J5A. The MC68HRC05J5A is functionally identical to the MC68HC05J5A with the exception that the MC68HRC05J5A supports the RC oscillator only, as outlined in Appendix A ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION VDD = 5V ±10 Figure A-2. Typical Internal Operating Frequency for RC Oscillator Connections A.3 ELECTRICAL CHARACTERISTICS Table A-1. Functional Operating Range Characteristic Operating Temperature Range Operating Voltage Range Table A-2. DC Electrical Characteristics Characteristic Supply Current 3 RUN ...
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... Freescale Semiconductor, Inc. This appendix describes the MC68HC705J5A, the emulation part for MC68HC05J5A. The entire MC68HC05J5A data sheet applies to the MC68HC705J5A, with exceptions outlined in this appendix. B.1 INTRODUCTION The MC68HC705J5A is an EPROM version of the MC68HC05J5A, and is avail- able for user system evaluation and debugging. The MC68HC705J5A is function- ally identical to the MC68HC05J5A with the exception of the 2560 bytes user ROM is replaced by 2560 bytes user EPROM ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION STOPMD — STOP Mode Option 1 = STOP mode is selected STOP mode is converted to HALT mode. IRQTRIG — IRQ, PA0-PA3 Interrupt Option 1 = Edge-triggered only Edge-and-level-triggered. PULLREN — Port A and B Pull-up/down Option 1 = Connected Disconnected PAINTEN — PA0-PA3 External Interrupt Option 1 = External interrupt capability on PA0-PA3 disabled ...
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... Freescale Semiconductor, Inc. $0000 0000 I/O 32 Bytes $001F 0031 0032 $0020 unimplemented 96 Bytes 0127 $007F 0128 $0080 User RAM 128 Bytes $00C0 0192 Stack 0255 $00FF unimplemented 0256 $0100 256 Bytes $0200 Mask Option Registers 1 & 2 $0201 unimplemented 0767 254 Bytes $02FF ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION B.4 BOOTSTRAP MODE Bootloader mode is entered upon the rising edge of RESET if the IRQ and the PB0 pin is at logic zero. The Bootloader program is masked in the TST ROM area from $0E00 to $0FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM ...
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... Freescale Semiconductor, Inc. B.5.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time t 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes. ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION B.6 ELECTRICAL CHARACTERISTICS Table B-1. Functional Operating Range Characteristic Operating Temperature Range Operating Voltage Range Table B-2. EPROM Programming Electrical Characteristics Characteristic Programming Voltage IRQ/V PP Programming Current IRQ/V PP Programming Time per byte Table B-3. DC Electrical Characteristics Characteristic Output Voltage ...
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... Freescale Semiconductor, Inc. Table B-3. DC Electrical Characteristics Characteristic Supply Current 3 RUN 4 WAIT 5 STOP LVR on LVR off I/O Ports Hi-Z Leakage Current PA0-7, PB0-5 (without individual pull-down/up activated) Input Pull-down Current PA0-5, PB0, PB3-5 (with individual pull-down activated) Input Pull-up Current RESET Input Current ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION B-8 For More Information On This Product, July 16, 1999 Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. This appendix describes the MC68HRC705J5A, the emulation part for MC68HRC05J5A, and a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J5A. The entire MC68HC05J5A data sheet and appendix B applies to the MC68HRC705J5A, with exceptions outlined in this appendix. C.1 INTRODUCTION The MC68HRC705J5A is a resistor-capacitor (RC) oscillator mask option version of the MC68HC705J5A (see Appendix B) ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION 6 5 VDD = 5V ±10 Figure C-2. Typical Internal Operating Frequency for RC Oscillator Connections C.3 ELECTRICAL CHARACTERISTICS Table C-1. Functional Operating Range Characteristic Operating Temperature Range Operating Voltage Range Table C-2. DC Electrical Characteristics Characteristic Supply Current ...
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... Freescale Semiconductor, Inc. ORDERING INFORMATION This section contains MC68HRC05J5A, MC68HC705J5A, and MC68HRC705J5A. D.1 MC ORDER NUMBERS Table D-1. MC Order Numbers Pin MC Order Number Count MC68HC05J5AJP 16 MC68HC05J5AJDW 16 MC68HC05J5AP 20 MC68HC05J5ADW 20 MC68HRC05J5AJP 16 MC68HRC05J5AJDW 16 MC68HRC05J5AP 20 MC68HRC05J5ADW 20 MC68HC705J5ACJP 16 MC68HC705J5ACP 20 MC68HC705J5ACDW 20 MC68HRC705J5ACJP 16 MC68HRC705J5ACP 20 MC68HRC705J5ACDW 20 NOTES extended temperature P = plastic dual-in-line package (PDIP small outline integrated circuit (SOIC) REV 2 ...
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... Freescale Semiconductor, Inc. GENERAL RELEASE SPECIFICATION D-2 For More Information On This Product, July 16, 1999 Go to: www.freescale.com MC68HC05J5A REV 2.1 ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center ...