mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet - Page 111

• Manufacturer Part Number: mc68hc11d0cfn2
• Description: M68hc11 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.5.2 Timer Interrupt Flag 2 Register
MC68HC711D3 — Rev. 2
MOTOROLA
NOTE:
RTII — Real-Time Interrupt Enable Bit
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits 3–2 — Unimplemented
PR1 and PR0 — Timer Prescaler Select Bits
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable
the corresponding interrupt sources.
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer
system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2
allow the timer subsystem to operate in either a polled or interrupt driven system.
Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits 3–0 — Not implemented
Address:
Refer to
Refer to
Always read 0.
Refer to
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to 1 at the end of every RTI period. To
clear RTIF, write a byte to TFLG2 with bit 6 set.
Refer to
Refer to
Always read 0.
Reset:
Read:
Write:
0 = RTIF interrupts disabled
1 = Interrupt requested
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8.7 Pulse
8.7 Pulse
Table
8.7 Pulse
8.7 Pulse
Bit 7
TOF
0
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
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8-4.
RTIF
Programmable Timer
6
0
Accumulator.
Accumulator.
Accumulator.
Accumulator.
PAOVF
5
0
PAIF
4
0
3
0
0
2
0
0
Programmable Timer
Real-Time Interrupt
1
0
0
Data Sheet
Bit 0
0
0
111