mc68hc705j2 Freescale Semiconductor, Inc, mc68hc705j2 Datasheet - Page 34

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mc68hc705j2

Manufacturer Part Number
mc68hc705j2
Description
8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC705J2
Bit test and branch instructions cause a branch based on the condition of any
readable bit in the first 256 memory locations. These three-byte instructions use
a combination of direct addressing and relative addressing. The direct address
of the byte to be tested is in the byte following the opcode. The third byte is the
signed offset byte. The CPU finds the conditional branch destination by adding
the third byte to the program counter if the specified bit tests true. The bit to be
tested and its condition (set or clear) is part of the opcode.
branching is from –128 to +127 from the address of the next location after the
branch instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register. Table 4-9 lists the jump and branch instructions.
Branch Always
Branch Never
Branch if Bit n of M = 0
Branch if Bit n of M = 1
Branch if Higher
Branch if Lower or Same
Branch if Carry Clear
Branch if Higher or Same
Branch if Carry Set
Branch if Lower
Branch if Not Equal
Branch if Equal
Branch if Half-Carry Clear
Branch if Half-Carry Set
Branch if Plus
Branch if Minus
Branch if Interrupt Mask Clear
Branch if Interrupt Mask Set
Branch if Interrupt Line Low
Branch if Interrupt Line High
Branch to Subroutine
Jump Unconditional
Jump to Subroutine
Table 4-9. Jump and Branch Instructions
CENTRAL PROCESSOR UNIT
Instruction
Mnemonic
BRCLR
BRSET
BHCC
BHCS
BEQ
BMS
BMC
BRA
BRN
BCS
BPL
BSR
JMP
JSR
BLS
BCC
BHS
BLO
BND
BHI
BMI
BIH
BIL
The span of
MOTOROLA
4-15

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