mc68194 ON Semiconductor, mc68194 Datasheet - Page 14

• Manufacturer Part Number: mc68194
• Description: Carrier Band Modem Cbm
• Manufacturer: ON Semiconductor

capacitor and resistor. The internal resistor R
used with or without an external resistor. A test pin is also
provided (SET−PW) to monitor the pulse width.
= 33 pF.
5.3 PHASE−LOCKED LOOP (PLL) COMPONENTS
active loop filter, a VCM, and a divide−by−4 feedback path.
Figure 5−4 shows the fundamental elements of the PLL with
their gain constants. The basic PLL allows the output
frequency ƒ
with a fixed phase relationship and to track it in frequency.
When “in lock” the inputs to the phase detector have zero
phase error. The input frequency is referenced to ƒ
following discussion a working knowledge of a PLL is
assumed.
information on PLL, the user is directed to Application Note
AN535.
where:
Figure 5−3 shows the arrangement of the external timing
For 5 Mbps operation, typically R
The PLL consists of a digital phase detector (PD), an
A PLL follows classic servo theory and equations. In the
∅
∅
G(s) = K
∅
e
o
∅
Figure 5−4. PLL Elements and Loop Equations
o
(s) = ( 1 / [ 1 + G(s) H(s)] ) ∅
NEEDED
(s) = ( G(s) / [ G(s) H(s)] ) ∅
(s)/4
i
(s)
ONLY
TEST
Figure 5−3. One−Shot Timing Components
FOR
ƒ
o
/4
CBM
DETECTOR
p
For
o
PHASE
K
to be “locked−on” to the input frequency ƒ
ƒ
K
p
K
PW
more
o
SET−PW
(TP)
R
∅
INT
H(s) = Kn
e
(s)
= 300 Ω
background
Reference: App Note AN535
B4
K
n
FILTER
K
i
ƒ
i
(s)
R
R
(s)
600 mV
PW
EXT
PW
and
= 1.5 kΩ and C
Kn = 1 / N = 1/4
C
PW
applications
INT
C
∅
VCM
K
EXT
o
o
+ 5 V
(s)
o
may be
/4.
http://onsemi.com
PW
ƒ
o
i
14
5.3.1 Phase Detector (PD)
phase difference between ∅
after filtering is used as the control signal for the VCM. The
PD has pump−up UP* and pump−down DOWN* outputs
with a typical 800 mV logic swing. UP* produces a low level
pulse equal in width to the amount of time the positive edge
of ∅
(VCM/4). DOWN* produces a low level pulse equal in
width to the amount of time the positive edge of ∅
∅
∅
When in−lock, both outputs produce a very narrow pulse or
negative spike.
note AN532A):
K
5.3.2 Voltage Controlled Multivibrator (VCM)
by the capacitor tied to pins VCM−C1 and VCM−C2. The
capacitor should be selected to put the desired operating
frequency in the center of the VCM tuning range.
where K
is found by:
then
5.3.3 Loop Filter
see reference AN535), the loop transfer function of Figure
5−4 takes the form:
relating it to the above form:
(filter transfer function) must take the form:
the desired results, where:
Figure 5−5B using an alternate approach of a charge pump.
The advantage of the charge pump design is that it can be
implemented using only a single 5.0 volt supply. Its transfer
function is:
K
p
o
o
The phase detector produces a voltage proportional to the
The gain of the phase detector is equal to (reference app
The operating frequency range of the VCM is determined
The transfer function of the VCM is given by:
Since a Type 2 system is required (phase coherent output,
G(s) H(s) = [K (s+a)] / s
Writing the loop transfer function (from Figure 5−4) and
G(s) H(s) = [K
Having determined K
K
An active filter of the form shown in Figure 5−5A gives
K
The active filter can also be implemented as shown in
v
/4. Both pulses will not occur on the same clock cycle as
/4 must either lead or lag ∅
= (Logic swing)/2π = 800 mV/2π = 0.127 V/radian
ƒ
ƒ
+
i
= (s+a) / s
= (R2 C s+1) / R1 C s (for large A)
K
(REF CLOCK) leads the positive edge of ∅
[(Upper frequency limit) – (Lower frequency limit)]2p
v
K
o
is the sensitivity in radians per second per volt. K
= 2π (nƒ)/(nV
o
= 2π (nƒ)/nV
= K
v
/s
p
(Control voltage tuning range)
K
v
K
n
K
p
ƒ
, K
CX
CX
] / s = [K (s+a)] / s
2
)s rad/s/V
i
o
(s) and ∅
rad/s/V
i
, and that K
when the PLL is out of lock.
o
(s)/4. This voltage
n
= 1/4 then K
2
i
lags
o
/4
v
ƒ