mpc853pzt80a Freescale Semiconductor, Inc, mpc853pzt80a Datasheet - Page 52

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mpc853pzt80a

Manufacturer Part Number
mpc853pzt80a
Description
Mpc853t Powerquicc Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
CPM Electrical Characteristics
1
2
52
Num
135
136
137
138
139
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
RSTRT active delay (from TCLK3 falling edge)
RSTRT inactive delay (from TCLK3 falling edge)
REJECT width low
CLKO1 low to SDACK asserted
CLKO1 low to SDACK negated
RENA(CD3)
CLSN(CTS1)
RCLK3
(Input)
(Input)
RxD3
(Input)
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Figure 50. Ethernet Collision Timing Diagram
Figure 51. Ethernet Receive Timing Diagram
Table 22. Ethernet Timing (continued)
2
Characteristic
2
121
124
120
125
121
126
123
Min
10
10
All Frequencies
1
Last Bit
127
Freescale Semiconductor
Max
50
50
20
20
Unit
CLK
ns
ns
ns
ns

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