mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 36

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

Local Bus
Table 32
bypassed.
36
Local bus clock to output high impedance
for LAD/LDP
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
2.All timings are in reference to LSYNC_IN for DLL enabled mode.
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
4.All signals are measured from OV
5.Input timings are measured at the pin.
6.The value of t
7.
8.Guaranteed by characterization.
9.Guaranteed by design.
Local bus cycle time
Internal launch/capture clock to LCLK delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
for inputs and t
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
case for clock one(1). Also, t
respect to the output (O) going invalid (X) or output hold time.
complementary signals at OV
for 3.3-V signaling levels.
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
describes the general timing parameters of the local bus interface of the MPC8560 with the DLL
LBOTOT
Parameter
Parameter
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
(First two letters of functional block)(reference)(state)(signal)(state)
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
Table 32. Local Bus General Timing Parameters—DLL Bypassed
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
LBKHOX
DD
DD
/2.
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV
symbolizes local bus timing (LB) for the t
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
POR Configuration
POR Configuration
(default)
(default)
—
—
—
—
—
—
—
—
Symbol
Symbol
t
(First two letters of functional block)(signal)(state) (reference)(state)
t
t
LBKSKEW
t
t
t
t
t
t
LBKHOZ2
LBKLOV1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBKHKT
LBOTOT
for outputs. For example, t
t
LBK
1
1
LBK
LBK
clock reference (K) goes high (H), in this
clock reference (K) to go high (H), with
Min
-1.8
-1.3
Min
6.0
2.3
5.7
5.6
1.5
—
—
—
Max
Max
150
-0.3
3.9
1.2
2.5
3.8
—
—
—
—
—
—
DD
LBIXKH1
Freescale Semiconductor
of the signal in question
Unit
Unit
symbolizes local
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
3, 9
4, 5
4, 5
4, 5
4, 5
7, 9
2
8
6
4