mpc860srzp50 Freescale Semiconductor, Inc, mpc860srzp50 Datasheet

no-image

mpc860srzp50

Manufacturer Part Number
mpc860srzp50
Description
Mpc860sar Powerquicc Features
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Technical Summar y
MPC860SAR/D
Rev. 0.1, 12/2001
MPC860SAR
PowerQUICC™ Technical
Summary
Advance Information
MPC860SAR Communication Controller Technical Summary
The MPC860SAR ATM communication controller is an enhanced version of the MPC860
PowerQUICC
includes support for asynchronous transfer mode (ATM).
ATM support includes all ATM layer functions and some AAL functions, including
segmentation and reassembly (SAR) for AAL5. The 860SAR also supports reception and
transmission of raw ATM cells directly to and from memory (also known as AAL0), enabling
other AAL protocols to be supported in software.
ATM traffic types directly supported include constant bit rate (CBR) and unspecified bit rate
(UBR), with a flexible hardware scheduler enabling implementation of other traffic types in
software, such as available bit rate (ABR).
The physical interface can be accomplished with the 860SAR by two methods. The first
method is via a standard UTOPIA port. The second method is serially, via any of the serial
communication controllers (SCCs) of the 860SAR. In addition to the ATM layer and AAL
layer functionality, the 860SAR also provides transmission convergence (TC) sublayer
functionality, modeled after the TC mapping of ATM cells into T1/E1 frames. Thus, the
860SAR can receive any serial ATM data stream with byte-aligned synchronization, including
T1, E1, and ADSL.
Like the other MPC860 devices, the MPC860SAR can be used in a variety of controller
applications, excelling particularly in communications and networking products that provide
WAN to LAN functionality. These include routers, ATM line card controllers, residential
broadband network interface units, and ADSL modem and infrastructure applications. The
integration of the high-performance MPC860 core and ATM SAR in the 860SAR also enables
the design of an ATM switch controller in a single part.
The 860SAR integrates two separate processing blocks, common with all MPC860 devices.
These are:
application programming
A RISC engine embedded in the communication processor module (CPM) which is
designed to provide the communications protocol processing provided by the
MPC860.
A high-performance core which can be used as a general-purpose processor for
family. In addition to all existing MPC860MH capabilities, the MPC860SAR

Related parts for mpc860srzp50

mpc860srzp50 Summary of contents

Page 1

Technical Summar y MPC860SAR/D Rev. 0.1, 12/2001 MPC860SAR PowerQUICC™ Technical Summary Advance Information MPC860SAR Communication Controller Technical Summary The MPC860SAR ATM communication controller is an enhanced version of the MPC860 PowerQUICC includes support for asynchronous transfer mode (ATM). ATM support ...

Page 2

In addition to ATM, the 860SAR also supports all of the performance and functionality of the MPC860MH, including multichannel HDLC and Ethernet. This is because the CPM of the 860SAR is based on the CPM of the MPC860MH. This enables ...

Page 3

Supports 53-byte 64-byte (expanded) ATM cells — AAL5 segmentation and reassembly (SAR) features for segmentation – Segment CPCS_PDU directly from system memory – CPCS_PDU padding – CRC32 generation – Automatic last cell marking (in PTI field ...

Page 4

System integration unit (SIU) — Hardware bus monitor — Spurious interrupt monitor — Software watchdog — Periodic interrupt timer — Low-power stop mode — Clock synthesizer — decrementer defined by the PowerPC Architecture — Time base and real-time clock ...

Page 5

Communications processor module (CPM) — Supports all functionality and performance of MPC860MH — RISC controller — Communication specific commands (e.g., graceful stop transmit, close receive buffer descriptor, RxBD) — 384 buffer descriptors — Supports continuous mode transmission ...

Page 6

Can be connected to the time-division-multiplexed (TDM) channels • One serial peripheral interface (SPI) — Supports master and slave modes — Supports multimaster operation on the same bus 2 ® • One I C (interprocessor-integrated circuit) port — Supports ...

Page 7

The 860SAR is comprised of three modules that use the 32-bit internal bus—embedded MPC860SAR core, system integration unit (SIU), and the communication processor module (CPM). See Figure 1. for the 860SAR block diagram. Instruction Bus Embedded MPC8xx Load/Store Core Bus ...

Page 8

Three special registers are available as scratch registers to support software table walk and update. The instruction cache is 4 Kbytes, two-way, set associative with physical addressing. It allows single-cycle access on hit with ...

Page 9

The PCMCIA interface is a master (socket) controller and is compliant with release 2.1. The interface supports up to two independent PCMCIA sockets requiring only external transceivers/buffers. It provides eight memory or I/O windows that can be allocated to the ...

Page 10

Low-power stop disables all logic in the processor except the minimum logic required to restart the device, and provides the lowest power consumption but requires the longest wake-up time. 1.4 ATM Support Support for asynchronous transfer mode (ATM) has been ...

Page 11

Support for expanded cells ( bytes) is also provided. While the standard size of cells on the ATM network is 53 bytes, support for larger cells enables the user to tag additional information onto a cell. An example ...

Page 12

DRAM SIMMs. Depending on the capacitance on the system bus, external buffers may be required. From a logic standpoint, however, a glueless system is maintained. PowerQUICC MPC860SAR CS0 OE WE0 Data Address CS7 WE[0–3] RAS2 RAS1 CAS[0–3] R/W ...

Page 13

... SCC1 (Ethernet) TDM a TDM b SMC Frequency Temperature (MHz) 25 0°C to 70°C 40 0°C to 70°C 50 0°C to 70°C TBD –40°C to 85°C SCC2 (ATM or HDLC; PPP or FUNI) SCC3 (ATM or HDLC; PPP or FUNI) Order Number MPC860SRZP25 MPC860SRZP40 MPC860SRZP50 TBD 13 ...

Page 14

The documents listed in Table 2. can be used as reference for the 860SAR. These documents can be obtained from the Literature Distribution Centers at the addresses listed on the back page. Visit the website for more information Document Title ...

Page 15

MOTOROLA MPC860SAR PowerQUICC™ Technical Summary 15 ...

Page 16

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon ...

Related keywords