mpc5604semlq Freescale Semiconductor, Inc, mpc5604semlq Datasheet - Page 8

• Manufacturer Part Number: mpc5604semlq
• Description: 32-bit Mcu For Cluster Applications With Stepper Motor, Tft Graphic Controller And Lcd Driver
• Manufacturer: Freescale Semiconductor, Inc

Overview
8
16-channel 2nd-generation Direct Memory
Access (eDMA)
AHB crossbar switch “lite” (XBAR-Lite)
Analog-to-digital converter (ADC)
Boot assist module (BAM)
Clock generation module (CGM)
Clock monitor unit (CMU)
Display control unit (DCU)
Deserial serial peripheral interface (DSPI)
QuadSPI (QSPI)
Enhanced modular input output system
(eMIOS)
Flash memory
FlexCAN (controller area network)
FMPLL (frequency-modulated phase-locked
loop)
Inter-integrated circuit (I
Interrupt controller (INTC)
JTAG controller
LCD driver module
LINflex controller
Memory protection unit (MPU)
Error Correction Status Module (ECSM)
Block
2
C™) bus
MPC560xS Microcontroller Data Sheet Data Sheet, Rev. 1
Preliminary—Subject to Change Without Notice
Table 2. MPC5606S Series Block Summary
Second-generation platform module capable of performing complex
data transfers with minimal intervention from a host processor via “n”
programmable channels
Internal busmaster
16-channel, 10-bit analog to digital converter
A block of read-only memory containing VLE code which is executed
according to the boot mode of the device
Provides logic and control required for the generation of system and
peripheral clocks
Monitors clock source (internal and external) integrity
Generates all signals required to drive a TFT LCD display, allowing
blending of data of up to 16 layers; can also display digital
video/graphics in the background plane
Provides a synchronous serial interface for communication with
external devices
Provides a synchronous serial bus for communication with external
serial flash memory and is optionally configurable as a third DSPI
module
Provides the functionality to generate or measure events
Provides non-volatile storage for program code, constants and
variables
Supports the standard CAN communications protocol
Two FMPLLs generate high-speed system clocks and support
programmable frequency modulation
A two wire bidirectional serial bus that provides a simple and efficient
method of data exchange between devices
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
Provides 40 × 4 (frontplane drivers × backplane drivers) or 6 × 38
driver configuration for driving LCD segments
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Provides hardware access control for all memory references
generated in a device
Provides miscellaneous control functions including program-visible
information about the platform configuration and revision levels, a
reset status register, wakeup control for exiting sleep modes, and
generic access error information for the processor core
Function
Freescale Semiconductor