mpc5602d Freescale Semiconductor, Inc, mpc5602d Datasheet - Page 6

• Manufacturer Part Number: mpc5602d
• Description: Mpc5602d Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Block diagram
Table 2
presence and number of blocks varies by device and package.
6
Analog-to-digital converter (ADC) Multi-channel, 12-bit analog-to digital-converter
Boot assist module (BAM)
Clock monitor unit (CMU)
Cross triggering unit (CTU)
Crossbar switch (XBAR)
Deserial serial peripheral interface
(DSPI)
Error Correction Status Module
(ECSM)
Enhanced Direct Memory Access
(eDMA)
Enhanced modular input output
system (eMIOS)
Flash memory
FlexCAN (controller area network) Supports the standard CAN communications protocol
Frequency-modulated
phase-locked loop (FMPLL)
Internal multiplexer (IMUX) SIU
subblock
Interrupt controller (INTC)
JTAG controller
LINFlex controller
Clock generation module
(MC_CGM)
Mode entry module (MC_ME)
Power control unit (MC_PCU)
summarizes the functions of all blocks present in the MPC5602D series of microcontrollers. Please note that the
Block
Preliminary—Subject to Change Without Notice
MPC5602D Microcontroller Data Sheet, Rev. 3.1
Table 2. MPC5602D series block summary
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Provides a synchronous serial interface for communication with external devices
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels.
Provides the functionality to generate or measure events
Provides non-volatile storage for program code, constants and variables
Generates high-speed system clocks and supports programmable frequency
modulation
Allows flexible mapping of peripheral interface on the different pins of the device
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Provides logic and control required for the generation of system and peripheral
clocks
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Function
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