mpc5668g Freescale Semiconductor, Inc, mpc5668g Datasheet
mpc5668g
Related parts for mpc5668g
mpc5668g Summary of contents
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... Supports 10-Mbps and 100-Mbps IEEE 802.3 MII, 10-Mbps 7-wire interface – IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition) • Media Local Bus (MLB) interface (MPC5668G only) – Supports 16 logical channels, max speed 1024 Fs • Interrupt controller (INTC) supports 316 external interrupt vectors (22 are reserved) • ...
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... ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.4 VRC Electrical Specifications . . . . . . . . . . . . . . . . . . . .30 4.5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30 4.6 Operating Current Specifications 4.7 I/O Pad Current Specifications . . . . . . . . . . . . . . . . . . .34 4.7.1 I/O Pad V Current Specifications . . . . . . . .35 DD33 Table 1. MPC5668G/MPC5668E Comparison Feature Package 208 MAPBGA RAM with ECC MPU DMA Ethernet (FEC) MediaLB (MLB-DIM) FlexRay ADC (10-bit) Total Timer I/O (eMIOS200) Cross Trigger Unit (CTU) ...
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... SPC5668GF0AVMG MPC5668G 208 MAPBGA package 4 SPC5668GF0AVMJ MPC5668G 256 MAPBGA package 1 All packaged devices are PPC5668x, rather than MPC5668x or SPC5668x, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. ...
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... MPC5668x Block Diagrams 2 MPC5668x Block Diagrams Figure 1 shows a top-level block diagram of the MPC5668G device. DEBUG JTAG NDI MASTERS Nexus3(Z6) e200z650 Core NDI Nexus2+(Z0) MMU(32TLB) e200z0 Core FPU/SPE 32K Cache VLE 4/8 Way AIPS(0) Bridge eSCI 2 MB Flash 36 x ADC (ECC eMIOS ...
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Figure 2 shows a top level block diagram for the MPC5668E device. DEBUG JTAG NDI MASTERS Nexus3(Z6) e200z650 Core NDI Nexus2+(Z0) MMU(32TLB) e200z0 Core FPU/SPE 32K Cache VLE 4/8 Way AIPS(0) Bridge ADC ...
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Pin Assignments 3 Pin Assignments 3.1 208-ball MAPBGA Pin Assignments Figure 3 shows the 208-ball MAPBGA pin assignments PD0 PC12 A V PG1 SS PD2 PD1 PC11 B PG0 C PD3 PD4 PD14 PC14 D PD5 ...
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MAPBGA Pin Assignments Figure 4 shows the 256-ball MAPBGA pin assignments PD0 PC12 A V PG1 SS PD2 PD1 PC11 B PG0 PD3 PD4 PD14 PC14 C D PD5 PD6 PD15 ...
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Pin Assignments 3.3 Pin Muxing and Reset States Table 2 shows the signals properties for each pin on MPC5668x. For all port pins that have an associated SIU_PCRn register to control pin properties, the supported functions column lists the functions ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PA6 PA[ Port A GPI AN[6] 01 ADC Analog Input 10 — 11 — PA7 PA[ Port A ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PB0 PB[ Port B GPIO AN[16]/ANW 01 ADC Analog Input/Mux In 10 — 11 — PB1 PB[1] 17 ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PB10 PB[10 Port B GPIO AN[26] 01 ADC Analog Input PCS_B[4] 10 DSPI_B Peripheral Chip Select 11 — PB11 PB[11] ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PC4 PC[ Port C GPIO AN[36] 01 ADC Analog Input 10 — 11 — PC5 PC[ ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PC15 PC[15 Port C GPIO AN[47] 01 ADC Analog Input — 10 — MA[2] 11 ADC Ext. Mux Address Select ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PD9 PD[ Port D GPIO CNRX_E 01 FlexCAN_E Receive RXD_L 10 SCI_L Receive 2 SDA_C 11 I C_C ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PE3 PE[ Port E GPIO RXD_D 01 eSCI_D Receive eMIOS[28] 10 eMIOS Channel 11 — PE4 PE[ Port ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PE14 PE[14 Port E GPIO 2 SCL_A 01 I C_A Serial Clock PCS_D[2] 10 DSPI_D Peripheral Chip Select ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PF8 PF[ Port F GPIO SCK_C 01 DSPI_C Serial Clock 10 — 11 — PF9 PF[ Port F ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PG2 PG[ Port G GPIO PCS_D[1] 01 DSPI_D Peripheral Chip Select 2 SCL_C 10 I C_C Serial Clock ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PG13 PG[13] 109 00 Port G GPIO eMIOS[2] 01 eMIOS Channel FEC_TXD[1] 10 Ethernet Transmit Data AN[61] 11 ADC Analog Input PG14 ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PH7 PH[7] 119 00 Port H GPIO eMIOS[24] 01 eMIOS Channel FEC_RXD[3] 10 Ethernet Receive Data 11 — PH8 PH[8] ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PJ1 PJ[1] 129 00 Port J GPIO eMIOS[14] 01 eMIOS Channel PCS_A[5] 10 DSPI_A Peripheral Chip Select 11 — PJ2 PJ[2] 130 ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PJ12 PJ[12] 140 00 Port J GPIO eMIOS[03] 01 eMIOS Channel 10 — 11 — PJ13 PJ[13] 141 00 Port ...
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Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num PK6 PK[6] 150 00 Port K GPIO FR_B_RX 01 FlexRay B Receive Data PCS_B[1] 10 DSPI_B Peripheral Chip Select PCS_C[4] 11 DSPI_C ...
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Pin Assignments Table 2. MPC5668x Signal Properties (continued) GPIO Pin Supported 4 (PCR Name Functions 3 Num MDO11 MDO[11] — — Nexus Message Data Out EXTAL EXTAL — — Main Crystal Oscillator Input EXTCLK External Clock Input ...
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Power and Ground Supply Summary Pin Function Description Name V Internal Logic Power DD V External I/O Power DDE1 V DDE2 V DDE3 V DDE4 V Analog Power DDA V 3.3 V I/O Power DD33 V Media Local Bus ...
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Electrical Characteristics 4 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5668x. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not ...
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Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage ...
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Electrical Characteristics 4.2.1 General Notes for Specifications at Maximum Junction Temperature An estimation of the chip junction temperature, T where ambient temperature for the package ( junction to ambient thermal resistance ( θ ...
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R = junction to case thermal resistance ( θ case to ambient thermal resistance ( θ device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ...
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Electrical Characteristics 4.3 ESD Characteristics Characteristic ESD for Human Body Model (HBM) HBM Circuit Description ESD for Field Induced Charge Model (FDCM) Number of Pulses per pin: Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses 1 All ESD testing ...
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Spec Characteristic 6 3.3–5.0 V External I/O Supply Voltage 7 2.5 V – 3.3 V External I/O Supply Voltage (MLB) 8 3.3 V External I/O Supply Voltage (Nexus) 9 Pad Input High Voltage Hysteresis enabled Hysteresis disabled (IHA/SH/SHA/MH/MHA) Hysteresis disabled ...
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Electrical Characteristics 2 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 3 5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 4 6.4 V for 10 hours cumulative time, ...
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Spec Characteristic 5 V Current DDSYN V @ 3.0 V – 3.6 V DD33 Run mode Sleep mode 4 – Optional 4–40 MHz osc enabled w/ no clock 4 – Optional 4–40 MHz osc enabled w/ clock 6 V Current ...
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Electrical Characteristics 4.7 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. ...
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I/O Pad V Current Specifications DD33 The power consumption of the V supply is dependent on the usage of the pins on all I/O segments. The power consumption DD33 is the sum of all input and output pin V ...
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Electrical Characteristics 4.8 Low Voltage Characteristics Spec Characteristic 1 1 Power-on-Reset Assert Level 2 2 Low Voltage Monitor 3.3 V Assert Level De-assert Level 3 Low Voltage Monitor Synthesizer Assert Level De-assert Level 4 Low Voltage Monitor 3.0 V Low ...
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Table 14. 3.3 V High Frequency External Oscillator (continued) Spec Characteristic 8 Crystal manufacturer’s recommended capacitive load 9 Discrete load capacitance to be connected to EXTAL 10 Discrete load capacitance to be connected to XTAL 11 Startup Time 1 When ...
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Electrical Characteristics Table 17. 5V Low Frequency (128 kHz) Internal RC Oscillator Spec Characteristic 1 1 Frequency before trim 2 Frequency after loading factory trim 3 3 Application trim resolution 4 Application frequency trim step 5 Startup Time 1 Across ...
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The maximum frequency value is with frequency modulation disabled. If frequency modulation is enabled, the maximuum frequency value should be de-rated by the percentage of modulation enabled so that the maximum frequency is not exceeded. 3 “Loss of Reference ...
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Electrical Characteristics Table 20. Flash Program and Erase Specifications Spec Characteristic 6 256 KB Block Pre-program and Erase Time 7 Wait States Relative to System Frequency PFCRPn[RWSC] = PFCRPn[APC] = 0b000; PFCRPn[WWSC] = 0b01 PFCRPn[RWSC] = PFCRPn[APC] = 0b001; PFCRPn[WWSC] ...
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Table 22. Pad AC Specifications (5 Spec Pad Type 2 Medium 8 3 Fast 4 Input 1 These are worst case values that are estimated from simulation and not tested. The values in the table are ...
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Electrical Characteristics Table 23. De-rated Pad AC Specifications (3 Spec Pad Type 8 3 Fast 4 Input 1 These are worst case values that are estimated from simulation and not tested. The values in the table ...
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AC Timing 4.14.1 Reset and Boot Configuration Pins Table 24. Reset and Boot Configuration Timing Spec Characteristic 1 RESET Pulse Width 2 BOOTCFG Setup Time after RESET Valid 3 BOOTCFG Hold Time from RESET Valid RESET 2 BOOTCFG Figure ...
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Electrical Characteristics 4.14.3 JTAG (IEEE 1149.1) Interface Spec Characteristic 1 TCK Cycle Time 2 TCK Clock Pulse Width (Measured TCK Rise and Fall Times (40% – 70%) 4 TMS, TDI Data Setup Time 5 TMS, TDI Data ...
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TCK TMS, TDI TDO TCK JCOMP Freescale Semiconductor Preliminary—Subject to Change Without Notice Figure 10. JTAG Test Access Port Timing 9 Figure 11. JTAG JCOMP Timing MPC5668x Microcontroller Data Sheet, Rev. 3 Electrical Characteristics ...
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Electrical Characteristics TCK 11 Output Signals 12 Output Signals Input Signals 46 Preliminary—Subject to Change Without Notice 13 14 Figure 12. JTAG Boundary Scan Timing MPC5668x Microcontroller Data Sheet, Rev Freescale Semiconductor ...
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Nexus Debug Interface Spec Characteristic 1 MCKO Cycle Time 2 MCKO Duty Cycle 3 MCKO Low to MDO, MSEO, EVTO Data Valid 4 EVTI Pulse Width 5 EVTO Pulse Width 3 6 TCK Cycle Time 7 TCK Duty Cycle ...
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Electrical Characteristics TCK TMS, TDI TDO 48 Preliminary—Subject to Change Without Notice 8 9 Figure 14. Nexus TDI, TMS, TDO Timing MPC5668x Microcontroller Data Sheet, Rev Freescale Semiconductor ...
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Enhanced Modular I/O Subsystem (eMIOS) Spec Characteristic 1 eMIOS Input Pulse Width 2 eMIOS Output Pulse Width 1 eMIOS timing specified 3.0 – 5 DDE 2 This specification does not include the rise and ...
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Electrical Characteristics 4.14.6 Deserial Serial Peripheral Interface (DSPI) Spec Characteristic 1 DSPI Cycle Time Master (MTFE = 0) Slave (MTFE = 0) Master (MTFE = 1) Slave (MTFE = PCS to SCK Delay 3 3 After SCK ...
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PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 16. DSPI Classic SPI Timing — Master, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 17. DSPI ...
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Electrical Characteristics SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) SOUT SIN Figure 18. DSPI Classic SPI Timing — Slave, CPHA = 0 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) SOUT SIN Figure ...
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PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 20. DSPI Modified Transfer Format Timing — Master, CPHA = 0 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN SOUT Figure 21. ...
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Electrical Characteristics SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) SOUT SIN Figure 22. DSPI Modified Transfer Format Timing — Slave, CPHA = 0 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) SOUT SIN ...
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MLB Interface 4.14.7.1 Media Local Bus DC Electrical Characteristics Table 30 provides the DC electrical characteristics for the Media Local Bus interface. Table 30. Media Local Bus DC Electrical Characteristics Parameter Maximum Input Voltage Low Level Input Threshold High ...
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Electrical Characteristics Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs (continued) Spec Parameter 10 MLBSIG/MLBDAT output high impedance from MLBCLK low 3 11 Bus Hold time 12 MLBSIG/MLBDAT output valid from MLBCLK rising • Ground = ...
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The Controller can shut off MLBCLK to place MLB in a low-power state. 2 Pulse width variation is measured at 1. triggering on one edge of MLBCLK and measuring the spread on the other edge, measured in ...
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Electrical Characteristics RX_CLK (input) RXD[3:0] (inputs) RX_DV RX_ER Figure 26. MII Receive Signal Timing Diagram 4.14.8.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) The transmitter functions correctly TX_CLK maximum frequency of 25 MHz +1%. There is ...
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MII Async Inputs Signal Timing (CRS and COL) Table 35. MII Async Inputs Signal Timing Spec Characteristic M9 CRS, COL minimum pulse width 1 Output pads configured with SRC = 0b11. CRS, COL Figure 28. MII Async Inputs Timing ...
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Electrical Characteristics MDC (output) MDIO (output) MDIO (input) Figure 29. MII Serial Management Channel Timing Diagram 60 Preliminary—Subject to Change Without Notice M14 M10 M11 M12 M13 MPC5668x Microcontroller Data Sheet, Rev. 3 M15 Freescale Semiconductor ...
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Package Characteristics 5.1 Package Mechanical Data Figure 30. 208 MAPBGA Package Mechanical Drawing Freescale Semiconductor Preliminary—Subject to Change Without Notice MPC5668x Microcontroller Data Sheet, Rev. 3 Package Characteristics 61 ...
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Package Characteristics 62 Preliminary—Subject to Change Without Notice Figure 31. 208 MAPBGA Package Detail MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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Figure 32. 256 MAPBGA Package Mechanical Drawing Freescale Semiconductor Preliminary—Subject to Change Without Notice MPC5668x Microcontroller Data Sheet, Rev. 3 Package Characteristics 63 ...
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Package Characteristics 64 Preliminary—Subject to Change Without Notice Figure 33. 256 MAPBGA Package Detail MPC5668x Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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Revision History Table 37 describes the changes made to this document between revisions. Revision Date 0 April 2008 Preliminary release. 1 June 2008 Initial release: Advance Information. 2 Jan 2009 Release: Advance Information. 3 September 2009 Release: Advance Information, ...
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