mpc5674k Freescale Semiconductor, Inc, mpc5674k Datasheet
mpc5674k
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mpc5674k Summary of contents
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... This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Document Number: MPC5675K MPC5675K MAPBGA– ...
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... No 2 modules, 32 channels each 3 modules, 6 channels each 16-bit Data + Address or 32-bit Data with Address bus muxed Preliminary—Subject to Change Without Notice MPC5674K MPC5675K Harvard 0–180 MHz (+2% FM) 0–90 MHz (+2% FM) 64 entries (SoR) Yes Yes Yes (SoR) ...
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... Class 3+ (for cores and SRAM ports) See the T recommended operating condition in the device data sheet A Preliminary—Subject to Change Without Notice MPC5674K MPC5675K 1 module Optional 3 modules Yes (SoR) 4 modules 4 1 module Yes (SoR) ...
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Overview NOTES: 1 Sphere of Replication. 2 Does not include Test or Shadow Flash memory space. 3 Available only on 473-pin package. 4 DDR available only on 473 package. Other modules available as follows: EBI or DDR on 473 package. ...
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Block diagram Figure 1 shows a top-level block diagram of the MPC5675K device. ECSM_0 STM INTC SEMA4 Crossbar switch (XBAR_0) Memory protection unit SRAM with ECC Logic PBRIDGE PBRIDGE ADC – Analog-to-digital converter BAM – Boot assist module CMU ...
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Overview 1.3 Feature list • High-performance e200z7d dual core — 32-bit Power Architecture technology CPU — 180 MHz core frequency — Dual-issue core — Variable length encoding (VLE) — Memory management unit (MMU) with 64 entries — 16 ...
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FlexRay module (V2.1) with dual channel 128 message objects and Mbit/s — Fast Ethernet Controller (FEC) 2 — modules • Four 12-bit analog-to-digital converters (ADCs) — 22 input channels — Programmable ...
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Overview — IEEE 754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point • Long cycle time instructions (except for guarded loads) do not ...
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Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio ...
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Overview • Chip select and write/byte enable options as presented in the pin-muxing table in descriptions” • Configurable wait states (via chip selects) • Optional automatic CLKOUT gating to save power and reduce EMI 1.4.8 On-chip flash memory • Up ...
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SDR The controller has the following features: • Supports 3 64-bit wide AHB slave ports • Optimized timing for 32-byte bursts and single bead accesses on the AHB interface • Optimized timing for 8-byte and 16-byte bursts on the ...
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Overview — Modified SPI mode for interfacing to peripherals with longer setup time requirements • Support for Mbit/s in Slave Only Rx Mode 1.4.15 Serial communication interface module (LINFlex) The LINFlex on this device features the following: ...
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FlexCAN • 32 message buffers each • Full implementation of the CAN protocol specification, Version 2.0B • Programmable acceptance filters • Individual Rx filtering per message buffer • Short latency time for high priority transmit messages • Arbitration scheme ...
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Overview 1.4.20 Motor control (MOTC) peripherals The peripherals in this section can be used for general-purpose applications, but are specifically designed for motor control (MOTC) applications. 1.4.20.1 FlexPWM The pulse width modulator module (FlexPWM) contains three PWM channels, each of ...
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External ADC input, taking into account values set in ADC high and low limit registers • DMA support 1.4.20.2 Cross Triggering Unit (CTU) The CTU provides automatic generation of ADC conversion requests on user selected conditions without CPU load ...
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Overview — Double buffer (to capture rising edge and falling edge) — Separate prescaler for each counter — Selectable clock source — 0–100% pulse measurement — Rotation direction flag (Quad decoder mode) • Maximum count rate — Equals peripheral clock/2 ...
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Collection of test results • Configurable and graded fault control — Internal reactions (No internal reaction, NMI, Reset, or safe mode) — External reaction (failure is reported to the outside world via configurable output pins) 1.4.24 System Integration Unit ...
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Overview 1.4.26 Non-maskable interrupt (NMI) The non-maskable interrupt with de-glitching filter is available to support high priority core exceptions. 1.4.27 System Status and Configuration Module (SSCM) The SSCM on the MPC5675K features the following: • System configuration and status • ...
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Package pinouts and signal descriptions 2.1 Package pinouts Figure 2 shows the MPC5675K in the 257 MAPBGA package. MPC5675K in the 473 MAPBGA package VSS_ VSS_ VDD_ nexus nexus HV_IO HV_IO HV_IO MDO[5] ...
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Package pinouts and signal descriptions VSS_ VSS_ VDD_ A HV_IO HV_IO HV_IO VSS_ VSS_ mc_cgl B HV_IO HV_IO clk_out VDD_ nexus VSS_ C HV_IO MDO[15] HV_IO nexus nexus can1 D MDO[1] MDO[3] RXD nexus nexus flexray E ...
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VDD_ pdi TXD[3] HV_IO DATA[3] fec VSS_ pdi TX_ER HV_IO DATA[6] fec fec fec RX_CLK RXD[1] COL VDD_ fec fec HV_FLA RXD[2] MDC VDD_ VDD_ VDD_ LV_COR LV_COR LV_COR VSS_ VSS_ VSS_ LV_COR LV_COR LV_COR VSS_ ...
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Package pinouts and signal descriptions 2.2 Pin descriptions The following sections provide signal descriptions and related information about the functionality and configuration for this device. 2.2.1 Pad types Table 2 lists the pad types used on the MPC5675K. Pad Type ...
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Table 3. 257 MAPBGA supply pins (continued) Ball Ball Name Number B16 VDD_HV_IO C1 VDD_HV_IO G2 VDD_HV_IO M2 VDD_HV_IO P10 VDD_HV_IO P14 VDD_HV_IO T2 VDD_HV_IO T16 VDD_HV_IO L14 VDD_HV_DRAM_VREF D8 VDD_HV_FLA M1 VDD_HV_OSC D14 VDD_HV_PDI H16 VDD_HV_PDI U14 VDD_HV_PMU R7 ...
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Package pinouts and signal descriptions Table 3. 257 MAPBGA supply pins (continued) Ball Ball Name Number R3 VSS_HV_IO R15 VSS_HV_IO T1 VSS_HV_IO T17 VSS_HV_IO U1 VSS_HV_IO U2 VSS_HV_IO U16 VSS_HV_IO U17 VSS_HV_IO D9 VSS_HV_FLA P1 VSS_HV_OSC C15 VSS_HV_PDI J16 VSS_HV_PDI ...
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Table 5. 473 MAPBGA supply pins (continued) Ball Ball Name Number D20 VDD_HV_PDI G2 VDD_HV_IO H21 VDD_HV_DRAM_VTT H22 VDD_HV_DRAM L20 VDD_HV_IO L21 VDD_HV_DRAM_VTT L23 VDD_HV_DRAM M2 VDD_HV_IO M4 VDD_HV_IO P23 VDD_HV_DRAM R20 VDD_HV_DRAM_VREF T4 VDD_HV_IO U22 VDD_HV_DRAM V1 VDD_HV_OSC V2 ...
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Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins (continued) Ball Ball Name Number A2 VSS_HV_IO A22 VSS_HV_IO A23 VSS_HV_IO B1 VSS_HV_IO B2 VSS_HV_IO B14 VSS_HV_IO B23 VSS_HV_IO C3 VSS_HV_IO C21 VSS_HV_PDI D5 RESERVED D9 VSS_HV_IO D11 VSS_HV_IO ...
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Table 5. 473 MAPBGA supply pins (continued) Ball Ball Name Number AC2 VSS_HV_IO AC22 VSS_HV_IO AC23 VSS_HV_IO AA10 VSS_HV_ADV AC8 VSS_HV_ADR_23 AC13 VSS_HV_ADR_0 AC16 VSS_HV_ADR_1 G7 VSS_LV_COR G8 VSS_LV_COR G9 VSS_LV_COR G10 VSS_LV_COR G11 VSS_LV_COR G12 VSS_LV_COR G13 VSS_LV_COR G14 ...
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Package pinouts and signal descriptions Table 5. 473 MAPBGA supply pins (continued) Ball Ball Name Number J12 VSS_LV_COR J13 VSS_LV_COR J14 VSS_LV_COR J15 VSS_LV_COR J16 VSS_LV_COR J17 VSS_LV_COR K7 VSS_LV_COR K8 VSS_LV_COR K9 VSS_LV_COR K10 VSS_LV_COR K11 VSS_LV_COR K12 VSS_LV_COR ...
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System pins Table 7 shows the system pins for the MPC5675K in the 257 MAPBGA package. system pins for the MPC5675K in the 473 MAPBGA package. Ball Ball Name Number C4 fccu0 F[1] C10 JCOMP E1 Nexus MDO[0] E4 ...
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Package pinouts and signal descriptions Table 8. 473 MAPBGA system pins (continued) Ball Ball Name Number AC20 RESET_SUP AC21 VREG_INT_ENABLE MPC5675K Microcontroller Data Sheet Data Sheet, Rev Freescale Confidential Proprietary, NDA Required Weak pull Safe Mode during reset ...
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Pin muxing Table 9 shows the pin multiplexing for the MPC5675K in the 257 MAPBGA package. MPC5675K in the 473 MAPBGA package. Ball Ball Ball Name Alternate I/O Number Type A4 GPIO nexus A0: siul_GPIO[114] MDO[5] A1: _ A2: ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type A12 GPIO fec A0: siul_GPIO[211] RXD[0] A1: i2c1_clock A2: _ A3: _ A13 GPIO fec A0: siul_GPIO[198] MDIO A1: fec_MDIO A2: _ A3: dspi2_CS0 A14 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type B8 GPIO flexray A0: siul_GPIO[48] CA_TX A1: flexray_CA_TX A2: _ A3: _ B10 GPIO fec A0: siul_GPIO[214] RXD[3] A1: i2c1_data A2: _ A3: _ B11 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type C6 GPIO etimer0 A0: siul_GPIO[0] ETC[0] A1: etimer0_ETC[0] A2 GPIO etimer0 A0: siul_GPIO[1] ETC[1] A1: etimer0_ETC[1] A2 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type C17 GPIO pdi A0: siul_GPIO[128] CLOCK A1: flexpwm2_B[1] A2: _ A3: etimer1_ETC[3] D1 GPIO nexus A0: siul_GPIO[85] MDO[2] A1: _ A2: npc_wrapper_MDO[2] A3 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type D12 GPIO fec A0: siul_GPIO[210] RX_DV A1: flexray_DBG3 A2: etimer2_ETC[0] A3: dspi0_CS7 D13 GPIO fec A0: siul_GPIO[199] MDC A1: fec_MDC A2: _ A3: _ D16 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type E17 GPIO pdi A0: siul_GPIO[135] DATA[4] A1: flexpwm2_A[2] A2: _ A3: etimer1_ETC[4] F1 GPIO nexus A0: siul_GPIO[113] MDO[6] A1: _ A2: npc_wrapper_MDO[6] A3 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type G1 GPIO nexus A0: siul_GPIO[115] MDO[4] A1: _ A2: npc_wrapper_MDO[4] A3 GPIO dspi0 A0: siul_GPIO[37] SCK A1: dspi0_SCK A2: _ A3: sscm_DEBUG[5] G4 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type H4 GPIO dspi1 A0: siul_GPIO[5] CS0 A1: dspi1_CS0 A2: _ A3: dspi0_CS7 H14 GPIO pdi A0: siul_GPIO[143] DATA[12] A1: _ A2: _ A3: _ H15 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type J15 GPIO pdi A0: siul_GPIO[146] DATA[15] A1: pdi_SENS_SEL[0] A2: i2c2_data A3: _ J17 GPIO flexpwm0 A0: siul_GPIO[195] X[1] A1: flexpwm0_X[1] A2: ebi_D29 A3 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type K17 GPIO flexpwm0 A0: siul_GPIO[148] B[0] A1: _ A2: ebi_CLKOUT A3: flexpwm0_B[0] L1 GPIO nexus A0: siul_GPIO[90] EVTO_B A1: _ A2: npc_wrapper_EVTO_B A3 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type M14 GPIO flexpwm0 A0: siul_GPIO[152] B[2] A1: dramc_CAS A2: ebi_WE_BE_1 A3: flexpwm0_B[2] M15 GPIO TDI A0: siul_GPIO[21] A1: _ A2: _ A3: _ M17 GPIO ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type P5 GPIO etimer1 A0: siul_GPIO[45] ETC[1] A1: etimer1_ETC[1] A2 GPIO etimer1 A0: siul_GPIO[46] ETC[2] A1: etimer1_ETC[2] A2: ctu0_EXT_TGR A3 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type P17 GPIO flexpwm1 A0: siul_GPIO[163] B[1] A1: dramc_ADD[5] A2: ebi_ADD13 A3: flexpwm1_B[1] R4 GPIO dspi1 A0: siul_GPIO[55] CS3 A1: dspi1_CS3 A2: lin2_TXD A3: dspi0_CS4 R5 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type R17 GPIO flexpwm1 A0: siul_GPIO[165] B[2] A1: dramc_ADD[7] A2: ebi_ADD15 A3: flexpwm1_B[2] T3 GPIO dspi2 A0: siul_GPIO[12] SOUT A1: dspi2_SOUT A2 ...
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Table 9. 257 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type T14 GPIO lin0 A0: siul_GPIO[19] RXD A1: _ A2: i2c0_data A3: sscm_DEBUG[3] T15 GPIO etimer1 A0: siul_GPIO[4] ETC[0] A1: etimer1_ETC[0] A2 ...
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Ball Ball Ball Name Alternate I/O Number Type A4 GPIO nexus A0: siul_GPIO[114] MDO[5] A1: _ A2: npc_wrapper_MDO[5] A3 GPIO nexus A0: siul_GPIO[112] MDO[7] A1: _ A2: npc_wrapper_MDO[7] A3 GPIO nexus A0: siul_GPIO[110] MDO[9] A1: _ ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type A13 GPIO fec A0: siul_GPIO[204] TXD[3] A1: fec_TXD[3] A2: _ A3: dspi2_CS2 A15 GPIO pdi A0: siul_GPIO[134] DATA[3] A1: flexpwm2_X[1] A2: _ A3: _ A16 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type B4 GPIO can1 A0: siul_GPIO[14] TXD A1: can1_TXD A2 GPIO nexus A0: siul_GPIO[219] MDO[14] A1: _ A2: npc_wrapper_MDO[14] A3: can3_TXD B6 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type B13 GPIO fec A0: siul_GPIO[205] TX_ER A1: fec_TX_ER A2: dspi2_CS3 A3: _ B15 GPIO pdi A0: siul_GPIO[137] DATA[6] A1: flexpwm2_B[0] A2: _ A3: etimer1_ETC[1] B16 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type C5 GPIO flexray A0: siul_GPIO[50] CB_RX A1: _ A2: ctu1_EXT_TGR A3 GPIO etimer0 A0: siul_GPIO[43] ETC[4] A1: etimer0_ETC[4] A2 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type C14 GPIO fec A0: siul_GPIO[212] RXD[1] A1: dspi1_CS1 A2: etimer2_ETC[5] A3: _ C15 GPIO fec A0: siul_GPIO[206] COL A1: fec_COL A2: _ A3: lin1_TXD C16 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type D1 GPIO nexus A0: siul_GPIO[86] MDO[1] A1: _ A2: npc_wrapper_MDO[1] A3 GPIO nexus A0: siul_GPIO[84] MDO[3] A1: _ A2: npc_wrapper_MDO[3] A3 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type D19 GPIO pdi A0: siul_GPIO[130] FRAME_V A1: _ A2: _ A3: _ D21 GPIO dramc A0: siul_GPIO[155] BA[1] A1: dramc_BA[1] A2: ebi_BDIP A3: flexpwm1_A[0] D22 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type E23 GPIO dramc A0: siul_GPIO[156] BA[2] A1: dramc_BA[2] A2: ebi_CS0 A3: flexpwm1_B[0] F1 GPIO nexus A0: siul_GPIO[109] MDO[10] A1: _ A2: npc_wrapper_MDO[10] A3 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type G1 GPIO nexus A0: siul_GPIO[87] MCKO A1: _ A2: npc_wrapper_MCKO A3 GPIO nexus A0: siul_GPIO[111] MDO[8] A1: _ A2: npc_wrapper_MDO[8] A3 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type H4 GPIO nexus A0: siul_GPIO[91] EVTI_B A1: _ A2: leo_sor_proxy_EVTI_B A3: _ H20 GPIO dramc A0: siul_GPIO[176] D[2] A1: dramc_D[2] A2: ebi_D10 A3: ebi_ADD26 J1 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type J23 GPIO dramc A0: siul_GPIO[180] D[6] A1: dramc_D[6] A2: ebi_D14 A3: ebi_ADD30 K1 GPIO dspi0 A0: siul_GPIO[37] SCK A1: dspi0_SCK A2: _ A3: sscm_DEBUG[5] K2 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type L2 GPIO dspi2 A0: siul_GPIO[42] CS2 A1: dspi2_CS2 A2: lin3_TXD A3: can2_TXD L3 GPIO dspi2 A0: siul_GPIO[10] CS0 A1: dspi2_CS0 A2: _ A3: can3_TXD M1 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type N3 GPIO flexpwm0 A0: siul_GPIO[60] X[1] A1: flexpwm0_X[1] A2 GPIO flexpwm0 A0: siul_GPIO[100] B[2] A1: flexpwm0_B[2] A2: _ A3: _ N20 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type P4 GPIO flexpwm0 A0: siul_GPIO[102] A[3] A1: flexpwm0_A[3] A2: _ A3: _ P20 GPIO dramc A0: siul_GPIO[188] D[14] A1: dramc_D[14] A2: ebi_D22 A3: _ P21 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type T2 GPIO flexpwm1 A0: siul_GPIO[117] A[0] A1: flexpwm1_A[0] A2: _ A3: can2_TXD T3 GPIO flexpwm1 A0: siul_GPIO[120] A[1] A1: flexpwm1_A[1] A2: _ A3: can3_TXD T20 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type U20 GPIO dramc A0: siul_GPIO[164] ADD[6] A1: dramc_ADD[6] A2: ebi_ADD14 A3: flexpwm1_A[2] U21 GPIO dramc A0: siul_GPIO[170] ADD[12] A1: dramc_ADD[12] A2: ebi_D4 A3: ebi_ADD20 U23 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type W20 GPIO lin0 A0: siul_GPIO[19] RXD A1: _ A2: i2c0_data A3: sscm_DEBUG[3] W21 GPIO dramc A0: siul_GPIO[172] ADD[14] A1: dramc_ADD[14] A2: ebi_D6 A3: ebi_ADD22 W22 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type Y9 GPIO etimer1 A0: siul_GPIO[45] ETC[1] A1: etimer1_ETC[1] A2: _ A3: _ Y10 GPIO etimer1 A0: siul_GPIO[46] ETC[2] A1: etimer1_ETC[2] A2: ctu0_EXT_TGR A3: _ Y11 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type Y22 GPIO dramc A0: siul_GPIO[169] ADD[11] A1: dramc_ADD[11] A2: ebi_D3 A3: ebi_ADD19 Y23 GPIO dramc A0: siul_GPIO[163] ADD[5] A1: dramc_ADD[5] A2: ebi_ADD13 A3: flexpwm1_B[1] AA4 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type AA14 ANA adc0_adc1 — AN[12] AA15 ANA adc1 — AN[0] AA16 ANA adc1 — AN[2] AA17 ANA adc1 — AN[5] AA18 ANA adc1 — AN[7] ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type AB4 GPIO flexpwm1 A0: siul_GPIO[122] X[2] A1: flexpwm1_X[2] A2: etimer2_ETC[2] A3: dspi0_CS5 AB5 GPIO flexpwm1 A0: siul_GPIO[125] X[3] A1: flexpwm1_X[3] A2: etimer2_ETC[3] A3: dspi0_CS6 AB6 ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type AB15 ANA adc1 — AN[1] AB16 ANA adc1 — AN[3] AB17 ANA adc1 — AN[4] AB18 GPIO TDO A0: siul_GPIO[20] A1: jtagc_TDO A2: _ A3: ...
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Table 10. 473 MAPBGA pin multiplexing (continued) Ball Ball Ball Name Alternate I/O Number Type AC10 ANA adc0 — AN[1] AC11 ANA adc0 — AN[3] AC14 ANA adc0_adc1 — AN[14] Additional Inputs Analog Inputs siul_GPI[24] AN: adc0_AN[1] etimer0_ETC[5] siul_GPI[34] AN: ...
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Electrical characteristics 3.1 Introduction This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for this device. The “Symbol” column of the electrical parameter and timings tables may contain an additional column containing “SR”, ...
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Electrical characteristics Table 11. Absolute maximum ratings No. Symbol ADC supply voltage DD_HV_ADV ADC supply ground SS_HV_ADV Core supply voltage digital logic DD_LV_COR Core supply voltage ground digital ...
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Table 12. Recommended operating conditions No. Symbol Voltage regulator supply ground SS_HV_PMU Input/output supply voltage DD_HV_IO Input/output supply ground SS_HV_IO Flash supply voltage DD_HV_FLA Flash ...
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Electrical characteristics 3.4 Thermal characteristics Table 13. Thermal characteristics for package options No. Symbol Thermal resistance junction-to-ambient JA natural convection Thermal resistance junction-to-ambient JA natural convection Thermal resistance JMA junction-to-moving-air ambient ...
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The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink ...
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Electrical characteristics See Section 6, “Reference documents,” 3.5.2 Test parameters The following test parameters shall be used: Method 150 Ohm TEM In case of only narrow band disturbances the maximum of the results will not change. In case of broadband ...
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No. Symbol Static latch-up class 3.8 Power Management Controller (PMC) electrical characteristics 3.8.1 PMC electrical specifications This section contains electrical characteristics for the PMC. No. Symbol Nominal V DD_LV_COR RC 3 PorC CC POR ...
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Electrical characteristics Cd Figure 7. PMU mandatory external components Table 18. VRC SMPS recommended external devices Reference Part Description Designator Ca — Cb — Cd — Ce — Cl — D SS8P3L L — Q SUD50P04/SQD50P04 R — 3.9 Power ...
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Table 19. Power dissipation characteristics No. Symbol Parameter Maximum run I DD_LV_PLL each PLL Maximum run I DD_HV_FLA Flash Maximum run I DD_HV_OSC OSC Maximum run I DD_HV_ADV ...
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Electrical characteristics × Table 21. Main oscillator electrical characteristics No. Symbol Parameter 1 — SR Oscillator frequency Oscillator start-up time f XOSCHSSU Input high level CMOS IH Schmitt Trigger Input low ...
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NOTES: 1 PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and temperature. 3.14 ADC electrical characteristics The MPC5675K provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter. 4095 4094 4093 4092 ...
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Electrical characteristics into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being ...
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Figure 11. Transient behavior during sampling phase In particular two different transient periods can be distinguished: • A first and quick charge transfer from the internal capacitance C capacitance C occurs ...
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Electrical characteristics Of course, R shall be sized also according to the current limitation constraints, in combination L with R (source impedance) and R S and C , then the final voltage V S than V . Equation 17 must ...
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No. Symbol ADC clock frequency (depends on ADC CK configuration) (The duty cycle depends on AD_CK Sampling frequency Sample time ADC_S Evaluation time ADC_E 5 ...
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Electrical characteristics 5 See Figure 10 missing codes. MPC5675K Microcontroller Data Sheet Data Sheet, Rev Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
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Flash memory electrical characteristics 3.15.1 Program/Erase characteristics Table 25 shows the Code flash memory program and erase characteristics. Table 25. Code flash program and erase electrical specifications No. Symbol Double Word (64 bits) program time DWPROGRAM ...
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Electrical characteristics No. Symbol Parameter 1a P/E CC Number of program/erase cycles per block for over the 1b operating temperature range ( Retention CC Minimum data retention at 85 °C average ambient temperature NOTES: 1 Typical ...
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SRAM memory electrical characteristics 3.16.1 Read access timing Table 30. System SRAM memory read access timing No. Symbol Maximum frequency for system SRAM READ reading (system clock frequency 3 SYS_CLK) 3.17 GP pads specifications This section ...
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Electrical characteristics Table 31. GP pads DC electrical characteristics No. Symbol Input leakage current IL (all ADC input-only ports RESET, low level input voltage ILR RESET, high level input voltage IHR ...
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Data based on characterization results, not tested in production. 3.18 PDI pads specifications This section specifies the electrical characteristics of the PDI pads. Please refer to the tables in “Pin descriptions,” for a cross reference between package pins and ...
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Electrical characteristics 3.18.1 PDI pads electrical specifications (V Table 34. PDI pads DC electrical characteristics (V No. Symbol I/O supply voltage DD_HV_PDI CMOS input buffer high voltage (hysteresis IH_C enabled CMOS ...
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Table 36. PDI pads AC electrical characteristics (V No. Name 2 PDI Fast NOTES: L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay. 1 3.18.2 PDI pads electrical specifications (V Table 37. PDI pads ...
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Electrical characteristics Table 39. PDI pads AC electrical specifications (V No. Name 1 PDI Medium 2 PDI Fast NOTES H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay. 3.18.3 PDI pads electrical specifications ...
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Table 40. PDI pads DC electrical specifications (V No. Symbol Output low voltage OL Table 41. Drive current @ Pad Drive Mode PDI Fast All PDI Medium All NOTES defined as the current sourced ...
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Electrical characteristics 3.19 DRAM pad specifications This section specifies the electrical characteristics of the DRAM pads. Please refer to the tables in Section 2.2, “Pin descriptions,” DRAM pads feature list: • Driver — Configurable to support LPDDR half strength, LPDDR ...
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Table 44. Mode configuration for DRAM pads Configuration 011 100 101 110 111 NOTES: 1 Configuration is selected in the corresponding PCR registers of the SIUL. 3.19.1 DRAM pads electrical specifications Table 45. DRAM pads DC electrical specifications (V No. ...
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Electrical characteristics NOTES defined as the current sourced by the pad to drive the output defined as the current sunk by the pad to drive the output Table ...
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Table 49. Output drive current @ V Pad Name DRAM ACC DRAM DQ DRAM CLK NOTES defined as the current sourced by the pad to drive the output defined as the ...
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Electrical characteristics Table 51. DRAM pads DC electrical specifications (V No. Symbol Output low voltage OL NOTES: 1 BGA473: Termination voltage can be supplied via package pins. BGA257 Termination voltage internally tied as the BGA257 does not ...
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Table 53. DRAM pads AC electrical specifications (V No. Pad Name 1 DRAM ACC 2 DRAM DQ 3 DRAM CLK NOTES: L H signifies low-to-high propagation delay and H L signifies high-to-low propagation delay. 1 3.20 RESET characteristics ...
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Electrical characteristics Table 54. RESET pin characteristics (continued) No. Symbol RESET pulse is sure not to be filtered NFRST 3.21 Reset sequence This section shows the duration for different reset sequences. It describes the different reset sequences ...
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RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the MPC5675K internal reset circuitry. A high level on this pin can only be generated by an ...
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Electrical characteristics Reset Sequence Start Condition Reset Sequence Start Condition Figure 25. Functional Reset Sequence Short The reset sequences shown in Figure 24 driven low during these two reset sequences only if the corresponding functional reset source (which triggered the ...
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Table 56. Reset sequence trigger—reset sequence Reset Reset Sequence Sequence Start Trigger Condition All active I Section 3. internal 21.4.1, destructive “Internal reset sources VREG (LVDs or Mode” internal HVD E Section 3. during 21.4.2, power-up and “External during VREG ...
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Electrical characteristics 7 If RESET is configured for long reset (default) and if BIST is disabled via device configuration data stored in the shadow sector of the NVM RESET is configured for short reset. 9 Internal reset sequence ...
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V V Figure 27. External VREG Mode, RESET_SUP rises after V V LvdReg + 3.5% LvdReg – 3.5% V Figure 28. External VREG Mode, RESET_SUP rises with V In case RESET_SUP has reached a valid high level before V stable, ...
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Electrical characteristics 3.21.4.3 External Reset via RESET Figure 29 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of RESET as specified in V RESET_SUP Figure 29. Reset sequence start via RESET assertion ...
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Peripheral timing characteristics 3.22.1 SDRAM (DDR) The MPC5675K memory controller supports three types of DDR devices: • DDR-1 (SSTL_2 class II interface) • DDR-2 (SSTL_18 interface) • LPDDR/Mobile-DDR (1.8V I/O supply voltage) JEDEC standards define the minimum set of ...
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Electrical characteristics Table 58. DDR and DDR2 (DDR2-400) SDRAM timing specifications (continued) At recommended operating conditions with V No. Symbol DQS-DQ skew for DQS and associated DQ inputs DQSQ DQS window start position related ...
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MCK Command Address DQS (in) Figure 34 provides the AC test load for the DDR bus Output Z 0 3.22.2 IEEE 1149.1 (JTAG) interface timing Table 59. JTAG pin AC electrical characteristics No. Symbol ...
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Electrical characteristics NOTES 1 needs to be smaller than or equal to the system clock (SYS_CLK). TCK TCK TCK TCK 3 TCK TMS, TDI TDO MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 112 Freescale ...
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TCK Output Signals Output Signals Input Signals 3.22.3 Nexus timing No. Symbol MCKO cycle time MCKO MCKO duty cycle MDC MCKO Low to MDO, MSEO, EVTO data valid MDOV 4 t ...
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Electrical characteristics NOTES: 1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2 MDO, MSEO, and EVTO data is ...
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CLKOUT IRQ 1 2 3.22.5 FlexCAN timing No. Symbol FlexCAN design target transmit data rate CAN_TX FlexCAN design target receive data rate CAN_RX 3.22.6 DSPI timing No. Symbol Parameter DSPI cycle ...
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Electrical characteristics No. Symbol Parameter Data setup time for inputs SUI Data hold time for inputs Data valid (after SCK edge) SUO Data hold time for outputs ...
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PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 40. DSPI classic SPI timing—master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 41. DSPI classic SPI timing—master, CPHA = 1 MPC5675K Microcontroller Data Sheet ...
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Electrical characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 42. DSPI classic SPI timing—slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 43. DSPI classic SPI timing—slave, CPHA = 1 MPC5675K Microcontroller ...
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PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 44. DSPI modified transfer format timing—master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 45. DSPI modified transfer format timing—master, CPHA = 1 MPC5675K Microcontroller ...
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Electrical characteristics SS SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 46. DSPI modified transfer format timing—slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL=1) SOUT SIN Figure 47. DSPI modified transfer format timing—slave, CPHA = 1 ...
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SCK SCK (CPOL = 1) Master SOUT Master SIN PCSx 2 Figure 48. Example of non-continuous format (CPHA = 1, CONT = 0) SCK SCK (CPOL = 0) (CPOL = 0) SCK (CPOL = 1) Master SOUT ...
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Electrical characteristics Table 65. PDI electrical characteristics (continued) No. Symbol Input setup time PDI_IS Input hold time PDI_IH NOTES: 1 Data can be captured at both launching and capturing edge of PDI_CLK. PDI_CLOCK PDI_DATA[15:0] ...
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RX_CLK (input) RXD[3:0] (inputs) RX_DV RX_ER 3.22.8.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) The transmitter functions correctly TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the system clock ...
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Electrical characteristics 3.22.8.3 MII async inputs signal timing (CRS and COL) No. Parameter 9 CRS, COL minimum pulse width NOTES: 1 Output pads configured with SRC = 0b11. CRS, COL 3.22.8.4 MII serial management channel timing (MDIO and MDC) The ...
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MDC (output) MDIO (output) MDIO (input) Figure 54. MII serial management channel timing diagram 3.22.9 External Bus Interface (EBI) timing No. Symbol D_CLKOUT period D_CLKOUT duty cycle CDC D_CLKOUT rise ...
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Electrical characteristics No. Symbol D_CLKOUT posedge to output COV signal valid (output delay) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0: Input signal valid to D_CLKOUT CIS posedge (setup time) D_ADD[9:30] D_DAT[0:15] D_RD_WR ...
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V OL_F D_CLKOUT D_CLKOUT 5 Output DDE Bus 5 Output DDE Signal Output Signal MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required V OH_F 3 4 Figure ...
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Electrical characteristics D_CLKOUT Input Bus Input Signal V DDE ipg_clk D_CLKOUT D_ALE D_TS D_ADD/D_DAT MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 128 Freescale Confidential Proprietary, NDA Required DDE DDE ...
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I C Timing Table 71. I No. Symbol 1 — D Start condition hold time 2 — D Clock low time 4 — D Data hold time 6 — D Clock high time 7 — D Data setup ...
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Package characteristics 2 SCL 1 SDA 3.22.11 LINFlex timing The maximum bit rate is 1.875 MBit/s. 4 Package characteristics 4.1 Package mechanical data MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 130 Freescale Confidential Proprietary, NDA Required ...
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MAPBGA Figure 60. 257 MAPBGA mechanical data ( MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Package characteristics 131 ...
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Package characteristics Figure 61. 257 MAPBGA mechanical data ( MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 132 Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
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MAPBGA Figure 62. 473 MAPBGA package mechanical data ( MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Package characteristics 133 ...
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Package characteristics Figure 63. 473 MAPBGA package mechanical data ( MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 134 Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
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Figure 64. 473 MAPBGA package mechanical data ( MPC5675K Microcontroller Data Sheet Data Sheet, Rev. 3 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required Preliminary—Subject to Change Without Notice Package characteristics 135 ...
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Orderable parts 5 Orderable parts Device feature set Device revision F = FlexRay F0 = Fab and Mask Operating frequency Tape and reel status 1 = 150 MHz R = Tape and reel 2 = 180 MHz (blank) = Trays ...
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MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. 8. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, ...
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... Semiconductor, Inc. All other product or service names are the property of their All other product or service names are the property of their respective owners. respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. © Freescale Semiconductor, Inc. 2010. All rights reserved. MPC5675K Rev. 3 8/2010 ...