mpc5554mzp80r2 Freescale Semiconductor, Inc, mpc5554mzp80r2 Datasheet - Page 52

• Manufacturer Part Number: mpc5554mzp80r2
• Description: Mpc5554 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Revision History for the MPC5554 Data Sheet
52
Revision
Rev. 2.0
Rev. 2.0
Rev. 2.0
Table 7
Section 3.7.1, “Input Value of Pins During POR Dependent on
Section 3.7.3, “Power-Down Sequence (VRC33
ORed_POR to become ORed POR.
Table 22
EBI section: OE, RD_WR, TEA, BDIP, BG, BR, BB, and TSIZ[0:1].
Table 6
Page 2 and throughout: Replaced kilobytes with KB and megabytes with MB.
Table 1
to 135 MHz.
Table 6
Table 12
maximum values for: Crystal reference, External reference, and Dual controller entries. The
footnote reads:
‘The device operates correctly if the frequency remains within ± 5% of the specification limit. This
tolerance range allows for a slight frequency drift of the crystals over time. The designer must
thoroughly understand the drift margin of the source clock.’
To:
3.3 V (V
3.3 V (V
3.3 V (V
From: Although there are no power up/down sequencing requirements to prevent issues like
3.3 V (V
3.3 V (V
3.3 V (V
to:
3.3 V (V
3.3 V (V
3.3 V (V
3.3 V (V
To: There are no power up/down sequencing requirements to prevent issues such as latch-up,
From: To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG
are not treated as ones (1s) when POR negates, VDD33 must not lag VDDSYN and the
RESET pin power (VDDEH6) when powering the device by more than the VDD33 lag
specification in
pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the
VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33 lag
specification. This VDD33 lag specification only applies during power up. VDD33 has no
lead or lag requirements when powering down.
When powering the device, VDD33 must not lag VDDSYN and the RESET power pin
(VDDEH6) by more than the VDD33 lag specification listed in
accidentally selecting the bypass clock mode because the internal versions of PLLCFG[0:1]
and RSTCFG are not powered and therefore cannot read the default state when POR
negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both
by more than the VDD33 lag specification. This VDD33 lag specification only applies during
power up. VDD33 has no lead or lag requirements when powering down.
latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down
varies depending on power. Prior to exiting POR, the pads are in a high impedance state
(Hi-Z).
excessive current spikes, and so on. Therefore, the state of the I/O pins during power
up/down varies depending on which supplies are powered.
Power Sequence Pin Status for the Fast Pad: Changed preceding paragraph
VCR/POR Electrical Specifications – Added to Spec 2:
Orderable Part Numbers: Changed the maximum operating speed from 132 MHz
VCR/POR Electrical Specifications: Changed the order of the entries in spec 2 from:
Bus Operation Timing: Specs 7 and 8: Added the following signals to Specs 7 and 8 the
FMPLL Electrical Characteristics: Added footnote to Spec 1 on the minimum and
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
DDSYN
) POR negated (ramp down)
) POR asserted (ramp up)
) POR negated (ramp down)
) POR negated (ramp up)
) POR asserted (ramp down)
) POR asserted (ramp up)
) POR asserted (ramp up)
) POR negated (ramp up)
) POR asserted (ramp down)
) POR negated (ramp down)
Table
Table 28. MPC5554 Revision History (continued)
MPC5554 Microcontroller Data Sheet, Rev. 2.0
6. VDD33 individually can lag either VDDSYN or the RESET power
Substantive Change(s)
Grounded)” Deleted the underscore in
0.0
0.0
2.0
Min 0.0
2.0
2.0
0.0
0.0
2.0
Min 0.0
0.30 V
0.30 V
2.85 V
2.85 V
2.85 V
0.30 V
2.85 V
0.30 V
Max 0.30 V
Max 0.30
VDD33,” changed:
Table
6. This avoids
V
Freescale Semiconductor
02/07/07
3/12/07
3/19/07
Date