mpc5567mzq80 Freescale Semiconductor, Inc, mpc5567mzq80 Datasheet
mpc5567mzq80
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mpc5567mzq80 Summary of contents
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... The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP) instructions, beyond the original Power PC instruction set. © Freescale Semiconductor, Inc., 2007. All rights reserved. Document Number: MPC5567 Rev. 1.0, 11/2007 Contents 1 Overview ...
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Overview The MPC5500 family of parts contains many new features coupled with high performance CMOS technology to provide significant performance improvement over the MPC565. The host processor core of the MPC5567 also includes an instruction set enhancement allowing variable length ...
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... MPC5567MVZ80 MPC5567MVZ112 MPC5567MZP132 MPC5567MZP112 MPC5567MZP80 MPC5567MZQ132 MPC5567MZQ112 MPC5567MZQ80 1 All devices are PPC5567, rather than MPC5567 or SPC5567, until product qualifications are complete. Not all configurations are available in the PPC parts. 2 The lowest ambient operating temperature is referenced Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). ...
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Electrical Characteristics 3 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MCU. 3.1 Maximum Ratings Spec Characteristic 2 1 1.5 V core supply voltage 2 Flash program/erase voltage 4 ...
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Table 2. Absolute Maximum Ratings Spec Characteristic 28 Maximum solder temperature Lead free (Pb-free) Leaded (SnPb Moisture sensitivity level 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and ...
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Electrical Characteristics 5 Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 6 Thermal characterization ...
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At a known board temperature, the junction temperature is estimated using the following equation θ where junction temperature ( board temperature at the package perimeter ( B R ...
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Electrical Characteristics so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately wire extending from the junction. Place the thermocouple wire flat against the package case ...
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ESD (Electromagnetic Static Discharge) Characteristics Characteristic ESD for human body model (HBM) HBM circuit description ESD for field induced charge model (FDCM) Number of pulses per pin: Positive pulses (HBM) Negative pulses (HBM) Interval of pulses 1 All ESD ...
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Electrical Characteristics Table 6. VRC/POR Electrical Specifications (continued) Spec 9 Absolute value of slew rate on power supply pins Required gain at Tj: ÷ VRCCTL sys MAX ...
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When powering down, V and V RC33 capacitors internal and external to the device are already charged. When not powering up or down, no delta between V and V is required for the V RC33 DDSYN There are no power ...
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Electrical Characteristics therefore cannot read the default state when POR negates. V pin (V ), but cannot lag both by more than the V DDEH6 applies during power up only. V 3.7.2 Power-Up Sequence (V The 1 power ...
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Table 9. DC Electrical Specifications (T Spec Characteristic 2 8 Flash programming voltage 9 Flash read voltage 3 10 SRAM standby voltage 11 Clock synthesizer operating voltage 12 Fast I/O input high voltage 13 Fast I/O input low voltage 14 ...
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Electrical Characteristics Table 9. DC Electrical Specifications (T Spec Characteristic 27b Operating current 1.5 V supplies @ 114 MHz: V (including V max current) @1.65 V typical use DD DDF V (including V max current) @1.35 V typical use DD ...
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Table 9. DC Electrical Specifications (T Spec Characteristic 30 Operating current V supplies: DDE V DDEH1 V DDE2 V DDE3 V DDEH4 V DDE5 V DDEH6 V DDE7 V DDEH8 V DDEH9 12 31 Fast I/O weak pullup current 1.62–1.98 ...
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Electrical Characteristics 3 If standby operation is not required, connect V 4 Applies to CLKOUT, external bus pins, and Nexus pins. 5 Maximum average RMS DC current. 6 Average current measured on automotive benchmark. 7 Peak currents can be higher ...
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Figure 3 shows an approximate interpolation of the I different voltages and temperatures. The vertical lines shown at 25 the I specifications (27d) listed in DD_STBY 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 ...
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Electrical Characteristics 3.8.1 I/O Pad Current Specifications The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a segment. The ...
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I/O Pad V DD33 The power consumption of the V power consumption is the sum of all input and output pin V pin V current can be calculated from DD33 (pad_fc) pins. The input pin V DD33 frequency, and ...
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Electrical Characteristics 3.9 Oscillator and FMPLL Electrical Characteristics (V DDSYN Spec Characteristic PLL reference frequency range: 2 Crystal reference (20) 3 Crystal reference (40 External reference (20) 3 External reference (40) Dual controller (1:1 mode System ...
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Table 12. FMPLL Electrical Specifications (continued) (V DDSYN Spec Characteristic CLKOUT period jitter, measured Peak-to-peak jitter (clock edge to clock edge) Long term jitter (averaged over interval) Frequency modulation range limit 20 (do not ...
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Electrical Characteristics 3.10 eQADC Electrical Characteristics Table 13. eQADC Conversion Specifications ( Spec Characteristic 1 ADC clock (ADCLK) frequency Conversion cycles 2 Differential Single ended 2 3 Stop mode recovery time 3 4 Resolution 5 INL: 6 MHz ADC clock ...
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H7Fa Flash Memory Electrical Characteristics Spec Table 14. Flash Program and Erase Specifications (T Spec Flash Program Characteristic 3 Doubleword (64 bits) program time 4 4 Page program time block pre-program and erase time 9 48 ...
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Electrical Characteristics Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device reference manual for definitions of these bit fields. Table 16. FLASH_BIU Settings vs. Frequency of Operation Maximum Frequency (MHz and including ...
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Table 17. Pad AC Specifications (V Spec Pad 3 Fast 4 Pullup/down (3.6 V max) 5 Pullup/down (5.5 V max) 1 These are worst-case values that are estimated from simulation (not tested). The values in the table are simulated at: ...
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Electrical Characteristics 3 The output delay, and the rise and fall, are calculated to 20% or 80% of the respective signal. 4 The output delay is shown in Figure system clock to the output delay. 5 This parameter is guaranteed ...
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RESET RSTOUT 3 PLLCFG BOOTCFG RSTCFG WKPCFG Figure 5. Reset and Configuration Pin Timing 3.13.2 IEEE 1149.1 Interface Timing Table 20. JTAG Pin AC Electrical Characteristics Spec Characteristic 1 TCK cycle time 2 TCK clock pulse width (measured at V ...
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Electrical Characteristics TCK 3 TCK TMS, TDI TDO 28 1 Figure 6. JTAG Test Clock Input Timing Figure 7. JTAG Test Access Port Timing MPC5567 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor ...
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TCK JCOMP Freescale Semiconductor 9 Figure 8. JTAG JCOMP Timing MPC5567 Microcontroller Data Sheet, Rev. 1.0 Electrical Characteristics 10 29 ...
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Electrical Characteristics TCK 11 Output signals 12 Output signals Input signals 30 14 Figure 9. JTAG Boundary Scan Timing MPC5567 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor ...
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Nexus Timing Spec Characteristic 1 MCKO cycle time 2 MCKO duty cycle 3 MCKO low to MDO data valid 4 MCKO low to MSEO data valid 5 MCKO low to EVTO data valid 6 EVTI pulse width 7 EVTO ...
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Electrical Characteristics TCK TMS, TDI TDO 3.13.4 External Bus Interface (EBI) Timing Table 22 lists the timing information for the external bus. Characteristic and Spec Description 1 CLKOUT period 2 CLKOUT duty cycle 3 CLKOUT rise time 4 CLKOUT fall ...
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Characteristic and Spec Description CLKOUT positive edge to output signal invalid or Hi-Z (hold time) External bus interface CS[0:3] ADDR[8:31] DATA[0:31] 5 BDIP OE RD_WR TA TEA TS WE/BE[0:3] CLKOUT positive edge to output signal invalid or Hi-Z (hold time) ...
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Electrical Characteristics Characteristic and Spec Description CLKOUT positive edge to output signal valid (output delay) Calibration bus interface CAL_CS[0, 2:3] 6a CAL_ADDR[10:30] CAL_DATA[0:15] CAL_OE CAL_RD_WR CAL_TS CAL_WE/BE[0:1] Input signal valid to CLKOUT positive edge (setup time) External bus interface ADDR[8:31] ...
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Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + ...
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Electrical Characteristics CLKOUT 5 Output ÷ DDE bus 5 Output ÷ DDE signal Output signal Figure 13. Synchronous Output Timing MPC5567 Microcontroller Data Sheet, Rev. 1.0 ÷ DDE 5 ÷ 2 ...
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CLKOUT Input bus Input ÷ 2 signal V DDE 3.13.5 External Interrupt Timing (IRQ Signals) Spec Characteristic 1 IRQ pulse-width low 2 IRQ pulse-width high 2 3 IRQ edge-to-edge time 1 IRQ timing specified at 3.0–5.5 V and ...
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Electrical Characteristics IRQ 1 3.13.6 eTPU Timing Spec Characteristic 1 eTPU input channel pulse width 2 eTPU output channel pulse width 1 eTPU timing specified at 3.0–5.5 V and T DDEH 2 This specification does not include the ...
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Timing Spec 1 eMIOS input pulse width 2 eMIOS output pulse width 1 eMIOS timing specified at 3.0–5.5 V and T DDEH 2 This specification does not include the rise and fall times. When calculating the ...
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Electrical Characteristics Spec Characteristic Data setup time for inputs Master (MTFE = 0) 9 Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Data hold time for inputs Master (MTFE = 0) 10 Slave ...
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PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 18. DSPI Classic SPI Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 19. DSPI Classic SPI Timing—Master, CPHA = 1 Freescale Semiconductor 2 4 ...
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Electrical Characteristics SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 20. DSPI Classic SPI Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 21. DSPI Classic SPI Timing—Slave, CPHA = ...
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PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 22. DSPI Modified Transfer Format Timing—Master, CPHA = 0 PCSx SCK output (CPOL=0) SCK output (CPOL=1) SIN SOUT Figure 23. DSPI Modified Transfer Format Timing—Master, CPHA = 1 Freescale Semiconductor ...
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Electrical Characteristics SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 24. DSPI Modified Transfer Format Timing—Slave, CPHA = 0 SS SCK input (CPOL=0) SCK input (CPOL=1) SOUT SIN Figure 25. DSPI Modified Transfer Format Timing—Slave, CPHA = 1 ...
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SSI Timing Table 27. EQADC SSI Timing Characteristics Spec Rating ÷ 2 FCK period ( FCK FCK 3 Clock (FCK) high time 4 Clock (FCK) low time 5 SDS lead / lag time 6 SDO ...
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Electrical Characteristics 3.14 Fast Ethernet AC Timing Specifications Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic (TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC signals are independent ...
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MII FEC Transmit Signal Timing FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, FEC_TX_CLK The transmitter functions correctly up to the FEC_TX_CLK maximum frequency of 25 MHz plus one percent. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed ...
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Electrical Characteristics 3.14.3 MII FEC Asynchronous Inputs Signal Timing FEC_CRS and FEC_COL Table 30 lists MII FEC asynchronous input signal timing. Table 30. MII FEC Asynchronous Inputs Signal Timing Spec 9 FEC_CRS, FEC_COL minimum pulse width Figure 30 shows MII ...
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FEC_MDC (output) FEC_MDIO (output) FEC_MDIO (input) Figure 31. MII FEC Serial Management Channel Timing Diagram Freescale Semiconductor MPC5567 Microcontroller Data Sheet, Rev. 1.0 Electrical Characteristics 15 49 ...
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Mechanicals 4 Mechanicals 4.1 MPC5567 324 PBGA Pinouts Figure pinout for the MPC5567 324 PBGA package VSSA1 A VSS VDD VSTBY AN37 AN11 VDDA1 AN16 B VDD33 VSS VDD AN36 AN39 ...
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MPC5567 416 PBGA Pinouts Figure pinout for the MPC5567 416 PBGA package. While the MPC5567 and the MPC5553/MPC5554 are pin-compatible, the MPC5567 ball map is shown here to highlight the balls that are not connected to ...
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Mechanicals VSS VSTBY AN37 B VDD VSS AN36 C VDD33 VDD VSS ETPUA ETPUA D VDD 30 31 ETPUA ETPUA VDDEH ETPUA ETPUA ETPUA ETPUA ETPUA ETPUA G ...
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ETRIG VSSA0 AN15 NC 1 ETRIG VSSA0 AN14 NC 0 VDDA0 AN13 NC NC VDDEH FEC_ AN12 NC 9 COL VDDE7 VDDE7 VDDE7 VDDE7 VSS VSS VSS VDDE7 VSS VSS VSS VDDE7 VSS VSS VSS VDDE7 ...
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Mechanicals 4.3 MPC5567 324-Pin Package Dimensions The package drawings of the MPC5567 324-pin TEPBGA package are shown in 54 Figure 35. MPC5567 324 TEPBGA Package MPC5567 Microcontroller Data Sheet, Rev. 1.0 Figure 35. Freescale Semiconductor ...
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Figure 35. MPC5567 324 TEPBGA Package (continued) Freescale Semiconductor MPC5567 Microcontroller Data Sheet, Rev. 1.0 Mechanicals 55 ...
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Mechanicals 4.4 MPC5567 416-Pin Package Dimensions The package drawings of the MPC5567 416 pin TEPBGA package are shown in 56 Figure 36. MPC5567 416 TEPBGA Package MPC5567 Microcontroller Data Sheet, Rev. 1.0 Figure 36. Freescale Semiconductor ...
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Figure 36. MPC5567 416 TEPBGA Package (continued) Freescale Semiconductor MPC5567 Microcontroller Data Sheet, Rev. 1.0 Mechanicals 57 ...
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Revision History for the MPC5567 Data Sheet 5 Revision History for the MPC5567 Data Sheet The history of revisions made to this data sheet are described in this section. The changes are divided into each revision of this document, and ...
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Table 32. Global and Text Changes Between Rev. 0.0 and 1.0 (continued) Location Section 3.7.1, “Input Value of Pins During POR Dependent on Added the following text directly before this section and after Power-on Sequence: ‘The values in Table 7 ...
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Revision History for the MPC5567 Data Sheet Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 2 Absolute Maximum Ratings: • Deleted Spec 3, “Flash core voltage.” • Spec 12 “DC Input Voltage”: Deleted from ...
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Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 5 ESD Characteristics: Added (Electromagnetic Static Discharge) in the table title. Table 6, VCR/POR Electrical Specifications: • Added footnote 1 to specs 1, 2, and 3 ...
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Revision History for the MPC5567 Data Sheet Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 8 Power Sequence Pin Status for Medium/Slow Pads: • Changed title to Pin Status for Medium and Slow Pads ...
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Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 12 FMPLL Electrical Characteristics: • Added ( – the end of the second line in the table title ...
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Revision History for the MPC5567 Data Sheet Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 16 FLASH BIU Settings vs. Frequency of Operations: • ‘Added footnote 1 to the end of the table title, ...
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Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued) Location Table 23 External Interrupt Timing: • Footnote 1: Deleted ‘F ‘ and CL = 200 pF with SRC = 0b11.’ • Deleted second figure after table ‘External ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. All rights reserved. ...