mpc604e Freescale Semiconductor, Inc, mpc604e Datasheet - Page 20

• Manufacturer Part Number: mpc604e
• Description: Powerpc 604e-tm Risc Microprocessor Technical Summary
• Manufacturer: Freescale Semiconductor, Inc

The PowerPC architecture consists of the following layers, and adherence to the PowerPC architecture can
be measured in terms of which of the following levels of the architecture is implemented:
For more information, refer to the PowerPC RISC Microprocessor Family: The Programming
Environments user’s manual.
The 604e complies to all three levels of the PowerPC architecture. Note that the PowerPC architecture
defines additional instructions for 64-bit data types. These instructions cause an illegal instruction exception
on the 604e. PowerPC processors are allowed to have features that are implementation-specific features that
fall outside, but do not conflict with, the PowerPC architecture specification. Examples of features that are
specific to the 604e include the performance monitor and nap mode.
2.1.1 Registers and Programming Model
The PowerPC architecture defines register-to-register operations for most computational instructions.
Source operands for these instructions are accessed from the registers or are provided as immediate values
embedded in the instruction opcode. The three-register instruction format allows specification of a target
register distinct from the two source operands. Load and store instructions transfer data between registers
and memory.
During normal execution, a program can access the registers, shown in Figure 6, depending on the
program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit in the machine
state register (MSR)). Note that registers such as the general-purpose registers (GPRs) and floating-point
registers (FPRs) are accessed through operands that are part of the instructions. Access to registers can be
explicit (that is, through the use of specific instructions for that purpose such as Move to Special-Purpose
Register (mtspr) and Move from Special-Purpose Register (mfspr) instructions) or implicitly as the part of
the execution of an instruction. Some registers are accessed both explicitly and implicitly.
The numbers to the left of the SPRs indicate the number that is used in the syntax of the instruction operands
to access the register.
Figure 6 shows the registers implemented in the 604e, indicating those that are defined by the PowerPC
architecture and those that are 604e-specific. Note that these are all of these registers except the FPRs are
32-bits wide.
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PowerPC user instruction set architecture (UISA)—Defines the base user-level instruction set, user-
level registers, data types, floating-point exception model, memory models for a uniprocessor
environment, and programming model for a uniprocessor environment.
PowerPC virtual environment architecture (VEA)—Describes the memory model for a
multiprocessor environment, defines cache control instructions, and describes other aspects of
virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may
not necessarily adhere to the OEA.
PowerPC operating environment architecture (OEA)—Defines the memory management model,
supervisor-level registers, synchronization requirements, and the exception model.
Implementations that conform to the OEA also adhere to the UISA and the VEA.
PowerPC 604e RISC Microprocessor Technical Summary