pcx7448vgh1250nc ETC-unknow, pcx7448vgh1250nc Datasheet
pcx7448vgh1250nc
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pcx7448vgh1250nc Summary of contents
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Datasheet Features • 3000 Dhrystone 2.1 MIPS at 1.3 GHz • Selectable Bus Clock (30 CPU Bus Dividers up to 28x) • Selectable MPx/60x Interface Voltage (1.5V; 1.8V; 2.5V) • P Typically 10W at 1.25 GHz Full ...
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Overview The PC7448 is the sixth implementation of fourth-generation (G4) microprocessors from Freescale The PC7448 implements the full PowerPC 32 bits architecture and is targeted at networking and com- puting systems applications. The PC7448 consists of a processor core ...
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Figure 1-1. PC7448 Block Diagram e2v semiconductors SAS 2009 PC7448 3 0814G–HIREL–04/09 ...
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Note that the PC7448 is a footprint-compatible, drop-in replacement in an PC7447A application if the core voltages are identical. 2. Features This section summarizes features of the PC7448 implementation of the PowerPC architecture. Major features of the PC7448 are as ...
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Vector Permute Unit (VPU) – Vector Integer Unit 1 (VIU1) handles short-latency AltiVec vector add instructions (for example, vaddsbs, vaddshs, and vaddsws) – Vector Integer Unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions ...
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Retires as many as three instructions per clock cycle • Separate on-chip L1 instruction and data caches (Harvard architecture) 32-Kbyte, eight-way set-associative instruction and data caches Pseudo Least-Recently-Used (PLRU) replacement algorithm 32-byte (eight-word) L1 cache block Physically indexed/physical tags Cache ...
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The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs The L2 cache is fully pipelined to provide 32 bytes per clock every other cycle to the L1 caches As many as 16 out-of-order ...
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Comparison with the PC7447A and PC7447 Table 3-1 compares the key features of the PC7448 with the key features of the earlier PC7447A and PC7447. All are based on the PC7450 RISC microprocessor and are architecturally very similar. The ...
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Table 3-1. Microarchitecture Comparison (Continued) Microarchitectural Specs Integer multiply (32 ×8, 32 ×16, 32 ×32) Scalar float VSFX (vector simple) VCFX (vector complex) VFPU (vector float) VPER (vector permute) TLBs (instruction and data) Tablewalk mechanism Instruction BATs/data BATs Size Associativity ...
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General Parameters The following list summarizes the general parameters of the PC7448: Table 4-1. Device Parameters Parameter Technology Die size Transistor count Logic design Packages Core power supply I/O power supply 5. Electrical and Thermal Characteristics This section provides ...
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DC Electrical Characteristics The tables in this section describe the PC7448 DC electrical characteristics. absolute maximum ratings. Table 5-1. Absolute Maximum Ratings Characteristic Core supply voltage PLL supply voltage I/O Voltage Mode = 1.5V Processor bus supply I/O Voltage ...
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The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OV ...
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V and AV may be reduced in order to reduce power consumption if further maximum core frequency constraints are DD DD observed. See Section ”” on page 4. Caution: Power sequencing requirements must be met; see 35. 5. See ...
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Table 5-5 provides the DC electrical characteristics for the PC7448. Table 5-5. DC Electrical Specifications (At Recommended Operating Conditions Characteristic Input high voltage (all inputs) Input low voltage (all inputs) Input leakage current ...
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Table 5-6 on page 15 document; see regarding power consumption when dynamic frequency switching is enabled, see ”Dynamic Frequency Switching (DFS)” on page Note: The power consumption information in this table applies when the device is operated at the nominal ...
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Voltage and Frequency Derating To reduce the power consumption of the device, these devices support voltage and frequency derating whereby the core voltage (V requirements are observed. The supported derated core voltage, resulting maximum processor core fre- quency (f ...
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Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:5] settings must be chosen such that the resulting SYSCLK (bus) fre- quency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the ...
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Processor Bus AC Specifications Table 5-9 provides the processor bus AC timing specifications for the PC7448 as defined in on page 19 and Figure 5-4 on page Table 5-9. Processor Bus AC Timing Specifications 12) Parameter Input setup times: ...
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The symbology used for timing specifications herein follows the pattern of t for outputs. For example, t ence)(state)(signal)(state) SYSCLK reference (K) going to the high (H) state or input setup time. And t high (H) until outputs (O) are ...
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Figure 5-5 provides the input/output timing diagram for the PC7448. Figure 5-5. Input/Output Timing Diagram SYSCLK All Inputs All Outputs (Except TS, ARTRY, SHD0, SHD1) All Outputs (Except TS, ARTRY, SHD0, SHD1) ARTRY, SHD0, SHD1 Note Midpoint Voltage ...
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IEEE 1149.1 AC Timing Specifications Table 5-10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in 22 through Figure 5-10 on page Table 5-10. JTAG AC Timing Specifications (Independent of SYSCLK) (At Recommended Operating Conditions, see Parameter ...
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Figure 5-7 provides the JTAG clock input timing diagram. Figure 5-7. JTAG Clock Input Timing Diagram TCLK Note Midpoint Voltage (OV Figure 5-8 provides the TRST timing diagram. Figure 5-8. TRST Timing Diagram Boundary Data Inputs Boundary Data ...
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Figure 5-10 provides the test access port timing diagram. Figure 5-10. Test Access Port Timing Diagram TDI, TMS Note Midpoint Voltage (OV e2v semiconductors SAS 2009 TCK VM t JLOV t JLOX TDO t JLOZ Output Data Valid ...
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Pin Assignments Figure 6-1 shows the pinout of the PC7448, 360 high coefficient of the thermal expansion ceramic ball grid array (HiTCE) package as viewed from the top surface. HiTCE package to indicate the direction of the top surface ...
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Pinout Listings Table 7-1 provides the pinout listing for the PC7448, 360 HiTCE package. The pinouts of the PC7448 and PC7447A are pin compatible, but the requirements regarding the use of the additional power and ground pins may change. ...
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Table 7-1. Pinout Listing for the PC7448, 360 HiTCE Package (Continued) Signal Name Pin Number CKSTP_OUT B1 CLK_OUT H2 R15, W15, T14, V16, W16, T15, U15, P14, V13, W13, T13, P13, U14, W14, R12, T12, W12, V12, N11, N10, R11, ...
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Table 7-1. Pinout Listing for the PC7448, 360 HiTCE Package (Continued) Signal Name Pin Number SMI F9 SRESET A2 SYSCLK A10 TA K6 TBEN E1 TBST F11 TCK C6 TDI B9 TDO A4 TEA L1 TEMP_ANODE N18 TEMP_CATHODE N19 TMS ...
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This pin can externally cause a performance monitor event. Counting of the event is enabled through software. 14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation. 15. ...
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Mechanical Dimensions for the PC7448, 360 HiTCE BGA Figure 8-1 on page 29 PC7448, 360 HiTCE BGA package. Figure 8-1. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7448, 360 HiTCE BGA Package D3 A1 CORNER ...
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Mechanical Dimensions for the PC7448, 360 HiTCE LGA Figure 8-1 provides the mechanical dimensions and bottom surface nomenclature for the PC7448, 360 HiTCE LGA package. Figure 8-2. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7448, 360 HiTCE LGA ...
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Mechanical Dimensions for the PC7448, 360 HiTCE RoHS-Compliant BGA Figure 8-1 on page 29 PC7448, 360 HiTCE BGA package with RoHS-compliant lead-free spheres. Figure 8-3. Mechanical Dimensions and Bottom Surface Nomenclature for the PC7448, 360 HiTCE RoHS-Compliant BGA Package ...
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System Design Information This section provides system and thermal design requirements and recommendations for successful application of the PC7448. 9.1 Clocks The following sections provide more detailed information regarding the clocking of the PC7448. 9.1.1 PLL Configuration The PC7448 ...
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Table 9-1. PC7448 Microprocessor PLL Configuration Example Bus-to-Core Core-to-VCO (5) PLL_CFG[0:5] Multiplier Multiplier 010000 2x 100000 3x 101000 4x 101100 5x 100100 5.5x 110100 6x 010100 6.5x 001000 7x 000100 7.5x 110000 8x 011000 8.5x 011110 9x 011100 9.5x 101010 ...
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The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7448; see tions” on page 16, for valid ...
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Power Supply Design and Sequencing The following sections provide detailed information regarding power supply design for the PC7448. 9.2.1 Power Supply Sequencing The PC7448 requires its power rails and clock to be applied in a specific sequence to ensure ...
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Figure 9-2. PC7448 Power Down Sequencing Requirements limit imposed by OV SYSCLK note also restrictions between SYSCLK and OV There is no requirement regarding AV within the RC time constant of the PLL filter ...
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Transient Specifications The ensure the long-term reliability of the device, the PC7448 requires that transients on the core power rail ( constrained. The recommended operating voltage specifications provided in DD page 12 are DC specifications. That is, ...
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Decoupling Recommendations Due to the PC7448 dynamic power management feature, large address and data buses, and high oper- ating frequencies, the PC7448 can generate transient power surges and high frequency noise in its power supply, especially while driving large ...
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Output Buffer DC Impedance The PC7448 processor bus drivers are characterized over process, voltage, and temperature. To mea- sure Z0, an external resistor is connected from the chip pad varied until the pad voltage is OV ...
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In addition, the PC7448 has one open-drain style output that requires a pull-up resistor (weak or stron- ger: 4.7–1 KΩ used by the system. This pin is CKSTP_OUT. BVSEL0 and BVSEL1 should not be allowed to float, ...
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The arrangement shown in or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0Ω. isolation resistor so that ...
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Figure 9-6. JTAG Interface Connection Board Sources KEY 13 No Pin 15 16 COP Connector Physical Pin Out Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is ...
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Thermal Management Information This section provides thermal management information for the high coefficient of thermal expansion (HiTCE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design, the heat sink, airflow, and thermal interface ...
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Figure 9-8. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options 9.7.1 Internal Package Conduction Resistance For the exposed-die packaging technology described in thermal resistance paths are as follows: • The die junction-to-case thermal resistance (the case is actually ...
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Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mecha- nism, Figure 9-10 (silicone, graphite/oil, ...
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There are several commercially available thermal interfaces and adhesive materials provided by the fol- lowing vendors: The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation ...
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During operation, the die-junction temperatures (T in Table 5-3 on page inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet- air temperature (T the range of 5° to 10° C. The thermal resistance ...
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Figure 9-11. Recommended Thermal Model of PC7448 Conductivity Silicon Bump and underfill (8.0 x 7 Substrate ( 1. Solder ball and air (25 ...
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Where Forward current Saturation current Voltage at diode Voltage forward biased Diode voltage while Diode voltage while Larger ...
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Power Consumption with DFS Enabled Power consumption with DFS enabled can be approximated using the following formula: Where Power consumption with DFS enabled DFS f = Core frequency with DFS enabled DFS f = Core frequency prior ...
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Bus-to-Core Multiplier Constraints with DFS DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:5] during hard reset. The complete listing is shown in Table 9-5. Valid divide Ratio Configurations Bus-to-Core Multiplier Configured by PLL_CFG[0:5] (see e2v ...
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Minimum Core Frequency Requirements with DFS In many systems, enabling DFS can result in very low processor core frequencies. However, care must be taken to ensure that the resulting processor core frequency is within the limits specified in on ...
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Document Revision History Table 12-1 provides a revision history for this hardware specification. Table 12-1. Document Revision History Revision Number e2v semiconductors SAS 2009 Date Substantive Change(s) 04/09 Table 10-1 on page ...
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PC7448 e2v semiconductors SAS 2009 ...
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Table of Contents Features..................................................................................................... 1 Description ................................................................................................ 1 Screening .................................................................................................. 1 1 Overview ................................................................................................... 2 2 Features .................................................................................................... 4 3 Comparison with the PC7447A and PC7447 ......................................... 8 4 General Parameters ............................................................................... 10 5 Electrical and Thermal Characteristics ............................................... 10 ...
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Ordering Information ............................................................................. 52 11 Definitions .............................................................................................. 52 11.1 Life Support Applications ..................................................................................... 52 12 Document Revision History .................................................................. 53 Table of Contents ...................................................................................... i ii 0814G–HIREL–04/09 PC7448 e2v semiconductors SAS 2009 ...
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How to reach us Home page: www.e2v.com Sales offices: Europe Regional sales office e2v ltd 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel: +44 (0)1245 493493 Fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 Burospace F-91572 Bièvres Cedex ...