dp83856 National Semiconductor Corporation, dp83856 Datasheet
dp83856
Related parts for dp83856
dp83856 Summary of contents
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... Larger repeaters with up to 372 ports may be constructed by cascading DP83850Cs together using the built-in Inter Repeater bus. In conjunction with a DP83856 100 Mb/s Repeater Infor- mation Base device, a DP83850C based repeater becomes a managed entity that is compatible with IEEE 802.3u (clause 30), collecting and providing an easy inter- face to all the required network statistics ...
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Block Diagram MANAGEMENT & INTER REPEATER BUS INTERFACE EE_CK EE_CS EE_DI EE_DO RDIR RDIO RDC /SDV GRDIO BRDC PART[5:0] Active Port # ACTIVITY[11:0] RXD[3:0], RX_ER, RXC, RX_DV TXD[3:0], TX_ER TXE[11:0] RXE[11:0] CRS[11:0] PHYSICAL LAYER INTERFACE 2 www.national.com ...
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... Hub ID 0 Register (HUBID0 4.10 Hub ID 1 Register (HUBID1 4.11 Port Management Counter Registers . . . . . . . . . 20 4.12 Silicon Revision Register (SIREV 5.0 DP83850C Applications . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 MII Interface Connections . . . . . . . . . . . . . . . . . . 21 5.2 Repeater ID Interface . . . . . . . . . . . . . . . . . . . . . 21 5.3 Inter Repeater Bus Connections . . . . . . . . . . . . 21 5.4 DP83856 100RIB Connections . . . . . . . . . . . . . . 25 5.5 Port Partition and Jabber Status LEDs . . . . . . . . 26 6.0 A.C. and D.C. Specifications . . . . . . . . . . . . . . . . . . . 27 6.1 D.C. Specifications . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 A.C. Specifications . . . . . . . . . . . . . . . . . . . . . . . 28 7.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 www.national.com ...
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Pin Connection Diagram IRD_ODIR 18 /IRD_ER 19 RSM3/RXECONFIG 20 21 RXD0 RXD1 22 RXD2 23 RXD3 24 RX_DV 25 26 RX_ER DP83850CVF RXC 27 GND 28 VCC 29 CRS0 30 CRS1 31 CRS2 32 CRS3 33 CRS4 34 CRS5 ...
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Pin Connection Diagram 1.1 Pin Table Pin Name /ACTIVEO /IR_ACTIVE /IR_BUS_EN /IR_COL_IN /IR_COL_OUT /IRD_ER /IRD_V /M_DV /M_ER /RST /SDV BRDC CRS[11:0] EE_CK EE_CS EE_DI EE_DO GND 1, 8, 16, 28, 46, 56, 66,76, 85, 94, 101, 111, 117,123 GRDIO ...
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Pin Descriptions 2.1 Physical Layer Interface Signal Name Type Active RXD[3:0] I — Receive Data: Nibble data inputs from each Physical layer chip ports are sup- ported. Note: Input buffer has a weak pull-up. RXE[11:0] O, ...
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... Note: Input buffer has a weak pull-up. MD[3:0] I/O/Z, M high Management Data: Outputs management information for the DP83856 manage- ment chip. During packet reception the DP83850C drives its RID number and the port number of the receiving port onto this bus. Note: Input buffer has a weak pull-up. ...
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Pin Descriptions (Continued) Signal Name Type Active /IR_BUS_EN O,L low Inter-Repeater Bus Enable: This signal is asserted at all times (either when the 100RIC is driving the bus or receiving from the bus) and it is deasserted only when ...
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Pin Descriptions (Continued) Signal Name Type Active PART[5: — Partition: Used to indicate each port's Jabber and Partition status. PART[3:0] cycle through each port number (0-11) continuously. PART[4] indicates the Partition status for each port (1 = ...
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Functional Description The following sections describe the different functional blocks of the DP83850C 100 Mb/s Repeater Interface Con- troller. The IEEE 802.3u repeater specification details a number of functions a repeater system is required to per- form. These functions ...
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Functional Description 3.6 Jabber Protection State Machine The jabber specification for 100BASE-T is functionally dif- ferent than 10BASE-T. In 10BASE-T, each port's Jabber Protect State machine ensures that Jabber transmissions are stopped after 5ms and followed ...
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... Management Event Flags and Counters Repeater management statistics are supported either directly by using the DP83850C's on-chip event flags and counters, or indirectly, by the DP83850C providing the information to the DP83856 via the management and transmit bus. Management information is maintained DP83850C in two ways: event fl ...
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... RDIO line after the line turn- around field's first bit. For unmanaged systems that do not use the DP83856 100RIB device for repeater management important to provide the 100RIC with a minimum of 3 cycles of RDC during device reset ...
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Functional Description Management CPU Bus Figure 3. Serial Management Addressing Scheme (Continued) phy_access = 0 ≈ ≈ phy_access = 1 phy_access = 0 14 ≈ ≈ ≈ ≈ ≈ ≈ www.national.com ...
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... Figure 3 shows a possible system implementation of the RDIO/GRDIO connection scheme. In this example, the DP83850C with address 00001 has its "phy_access" bit set, allowing its twelve DP83840 PHY devices to be accessed by the DP83856 100RIB. Table 1. Serial Register Interface Encoding Field Encoding <start> ...
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Registers The DP83850C has 64 registers in 2 pages of 32 16-bit registers. At power-on and/or reset, the DP83850C defaults to Page 0 registers. The register page can be changed by writing to the PAGE register in either register ...
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Registers (Continued) 4.2 Page 1 Register Map Address Name Access (hex) 0 CONFIG r/w Sets the DP83850C configuration (same as page 0 CONFIG register). 1 PAGE r/w Select either register page Reserved 3 ...
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Registers (Continued) Bit Bit Name Access D1 PHY_ACCESS r/w This bit allows the management agent to access the DP83840A PHY chip’s register via the MII serial protocol Note: When in PHY_access mode, RDIO will be driven by ...
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Registers (Continued) 4.7 Administration Register (ADMIN) Page 0 Address 4h Bit Bit Name Access D15 - D13 reserved - D12 TST_PART_LED r/w D11 - D0 ADMIN_DIS[11] ... r/w ADMIN_DIS[0] 4.8 Device ID Register (DEVICEID) Page 0 Address 5h Bit ...
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Registers (Continued) 4.10 Hub ID 1 Register (HUBID1) Page 0 Address 7h Bit Bit Name Access D15 - D0 HUB_ID1[15:0] r/w Hub ID 1: Contains the second 16 bits read from the EEPROM. The first bit read will be ...
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DP83850C Applications 5.1 MII Interface Connections The DP83850C's interface to DP83840A PHY devices is fully described in the Application Note – AN1069 "100BASE-TX Unmanaged Repeater Design Recommen- dations". Designers should be aware that there are signifi- cant issues involved ...
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DP83850C Applications is the BTL logic transceiver family: this approach has the advantage of significantly lower noise and may assist in successful passing of FCC and other EMI tests. Figure 8 shows the signal connections on the Inter-RIC bus. ...
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DP83850C Applications DP83850C 100RIC /ACTIVEO IR_VECT4 IR_VECT3 IR_VECT2 IR_VECT1 IR_VECT0 ABT125 /IR_ACTIVE ABT125 (Continued) F32 ABT125 F32 ABT125 F32 ABT125 F32 ABT125 F32 ABT125 Figure 8. Inter Repeater Bus Connections 23 ABT125 IR_VECT4_BP IR_VECT3_BP ABT125 IR_VECT2_BP ABT125 IR_VECT1_BP ABT125 ...
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DP83850C Applications DP83850C 100RIC 74F27 /ACTIVEO IRD_ODIR IRD3 IRD2 IRD1 IRD0 IRD_CK P /IRD_V /IRD_ER MD3 MD2 MD1 MD0 MD_CK P /MD_V /MD_ER P = Pull-Ups, 1.2k ohms (Continued) 74ABT16245C /OE DIR ...
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... VCC RDIO RDIR /SDV RDC Figure 10. Typical DP83850C to DP83856 Connections (Continued) known as the "Local 100RIC" since is likely to be the near- est one (physically) to the 100RIB on the circuit board. All the other signals that the 100RIB requires in order to keep statistics are common to all the other 100RICs. Figure 10 shows a typical connection between the 100RIC and the 100RIB ...
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DP83850C Applications 5.5 Port Partition and Jabber Status LEDs Port Partition and Jabber Status must be decoded from the PART[5:0] outputs as described in section 3.11. One possi- ble decoder implementation is shown in Figure 11. This uses 74LS259 ...
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A.C. and D.C. Specifications Absolute Maximum Rating and Recommended Operating Conditions Supply Voltage (Vdd) Supply voltage (Vdd) DC Input Voltage (Vin) -0 Vcc + 0.5 V Ambient Temperature (Ta) DC Output Voltage (Vout) -0 Vcc ...
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A.C. and D.C. Specifications 6.2 A.C. Specifications 6.2.1 Receive Timing T0 CRSx to RXEx assertion delay (Note 1) T1 CRSx to RXEx de-assertion delay with no collision T2 CRSx to RX_DV delay requirement (Note 2) T3 /IRD_V setup to ...
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A.C. and D.C. Specifications 6.2.2 Transmit, Partition and RID_ER Timing T7 TX_RDY delay from LCK high T8 TXE[11:0] delay from LCK high T9 TXD[3:0] or TX_ER valid time from LCK high T10 PART[5:0] valid time from LCK high T11 ...
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A.C. and D.C. Specifications 6.2.3 Inter Repeater Receive and Intra-Repeater Collision Timing T12 Receive to Inter Repeater Bus delay T12a Receive to Inter Repeater Bus skew T13 CRSx assertion (de-assertion) to -ACTIVEO assertion (de-assertion) T14 CRSx assertion (de-assertion) to ...
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A.C. and D.C. Specifications 6.2.4 Inter Repeater Collision Timing T19 IR_VECT[4:0] change to /IR_COL_OUT assertion[de-assertion] T20 /IR_COL_OUT assertion to IRD_ODIR de-assertion T20A /ACTIVEO low to IR_VECT[4:0] feedback Note 9: This timing refers to the condition where the repeater has ...
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A.C. and D.C. Specifications 6.2.6 Management Bus - Input Mode Timing T24 /M_DV setup to M_CK high T25 /M_DV hold from M_CK high T26 MD[3:0] or /M_ER setup to M_CK high T27 MD[3:0] or /M_ER hold from M_CK high ...
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A.C. and D.C. Specifications 6.2.7 Serial Register Write Timing T28 RDC period T29 12 RDC high time T30 12 RDC low time T31 RDC to BRDC delay T32 RDIO setup to RDC high T33 RDIO hold from RDC high ...
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A.C. and D.C. Specifications 6.2.8 Serial Register Read Timing T37 RDIO valid from RDC T38 14 GRDIO to RDIO delay Note 14:Serial data will be gated from GRDIO to RDIO during read operations when the “phy_access” bit in the ...
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A.C. and D.C. Specifications 6.2.9 EEPROM Access Timing T39 EE_SK period 15 T40 EE_SK high time 15 T41 EE_SK low time 15 T42 EE_CS assertion [de-assertion] from EE_SK low T43 EE_DI assertion [de-assertion] from EE_SK low T44 EE_DO setup ...
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A.C. and D.C. Specifications 6.2.10 Clocks, Reset and RID Timing T46 LCK period T47 LCK high time T48 LCK low time T48a LCK frequency tolerance 16 T49 /RST assertion time T50 RID[4:0] setup to LCK high T51 M_CK period ...
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Physical Dimensions inches (millimeters)unless otherwise noted 132-Lead Molded Plastic Quad Flat Package, JEDEC LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE ...