dp83856b National Semiconductor Corporation, dp83856b Datasheet
dp83856b
Related parts for dp83856b
dp83856b Summary of contents
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... DP83850s it enables a repeater system to become a single managed entity that is fully compatible with the IEEE 802.3u clause 30 management requirements. The DP83856B device incorporates all the necessary functions and counters for collecting network statistics. Information is gathered on a per-packet, per-port basis: the port which is receiving the packet is the active port for statistics collection ...
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Block Diagram Addr/Data TXD[3:0], T X_ER, TX_RDY, -IR_COL, -IRD_V, MD[3:0], M_CK, -M_DV, -M_ER Inter Repeater Bus 2 www.national.com ...
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Pin Connection Diagram 2.0 Pin Description 2.1 CPU Interface 2.2 SRAM Interface 2.3 Transmit Bus and Management Bus 2.4 MII Interface 2.5 Test Interface 2.6 Miscellaneous 2.7 Pin Type Designation 3.0 Functional Description 3.1 Statistics Generation 3.2 SRAM Interface ...
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... GND 4 6 VCC 4 7 -CCS 4 8 GND 4 9 VCC 5 0 DP83856B DP83856 100 Mb/s Repeater Information Base 132 pin PQFP (top view) Order Number DP83856BVF NS Package Number VF132A 4 116 -SDV 115 RRD IR 114 RDC 113 RDIO 112 VCC 111 GN D 110 RES1 ...
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... Signal Name Type -CINT O/Z, L -CRDY O/Z, L -CCS I CR-W I CA[7:1] I CD[15:0] I/O/Z, M 2.2 SRAM Interface The SRAM interface pins are used to connect the DP83856B to a fast (20ns) external SRAM. The DP83856B supports bit SRAM configuration. Signal Name Type SA[12:0] O/Z, L SD[15:0] I/O/Z/P, L SR-W O/Z,L -SCS O/Z, L -SOE O/Z, L Active Description ...
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... The DP83856B monitors this line at the beginning of the frame to establish whether the frame is a false carrier event. If TX_RDY is valid and -IR_DV is invalid when the DP83856B samples the -IR_DV line, then a false carrier event is counted. - Management Data [3:0]: Data which is sourced by any ...
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... Active Low Tri-State: Pulling this pin low puts the DP83856B into a test mode that tristates all outputs except -NAND_E and -NAND_O. This allows an external tester to drive all the outputs of the DP83856B. ...
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... DP83850 because the TX signals (to which the DP83856B must be synchronized) are all synchronous to the local clock. Must be a 25.000MHz, 40/60 duty cycle, 50ppm. Low Reset: The DP83856B is reset when this signal is asserted low. Asserting this signal will cause all DP83856B state machines and registers to enter their reset state. - Reserved Output 1: Leave unconnected ...
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... Repeater False Carrier Events Repeater Collisions (per port collision map obtained from DP83850s) 3.1.3 DP83850 Notified For a few of the required statistics the DP83856B has no way of determining the occurrence of that event. These statistics are obtained by notification from the connected DP83850s. DP83850 notified statistics include: ...
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... Figure 1. Memory Map for the DP83856 Statistics SRA M hardware implementation. All other statistics are stored in big endian mode. The DP83856B can be directly connected to the SRAM; there is no need for buffering between the DP83856B and the SRAM. The DP83856B requires fast SRAM with a maximum access time of 20ns ...
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... The "Invalid MII register read" interrupt is generated based on the DP83856B detecting an error while performing a read access. DP83856B looks for a leading 0 on reads does not see it, it flags the read as invalid and generates the interrupt. 3.5 MII Register Interface ...
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... DP83856B to a management CPU in the normal 16-bit manner with address bits A1 through A7 from the CPU connected to bits CA1 to CA7 on the DP83856B. The addresses are thus the offset from the base address at which the DP83856B is located in the system. Register ...
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Register Memory Map Continued Address 90h Repeater Collisions Hi Read 92h Repeater Collisions Lo Read 94h Network Utilization Hi Read 96h Network Utilization Lo Read 98h False Carrier Hi Read 9Ah False Carrier Lo Read 9Ch - 9Eh Reserved A0h ...
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... D(4:7) PAGE_SEL D(8:15) Reserved Access Description R/W 0: DP83856B writes 0 after register access completes. 1: CPU initiates register access by writing 1 This bit indicates when the current DP83850 or Physical Layer device register access is complete. R/W 0: DP83856B writes 0 after SRAM access completes. 1: CPU initiates SRAM access by writing 1. This bit indicates when the current SRAM access is complete ...
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... Enable MII access complete Interrupt. R/W 0: Mask SRAM access complete Interrupt. 1: Enable SRAM access complete Interrupt. R/W 0: Mask DP83856B error Interrupt. 1: Enable DP83856B error Interrupt. R/W 0: Mask MII Register Error Interrupt. 1: Enable MII Register Error Interrupt. This bit indicates the occurrence of an MII register read error. ...
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SRAM Interface Register Address: 06h Reset: All bits cleared to zero. Bit Bit Name D(0:4) STAT_ACC# D(5:6) Reserved D7 R/W_SRAM D(8:11) PORT_ACC# D(12:15) RIC_ACC# Note: This register should NOT be accessed while an SRAM access is in progress (If ...
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... REG_ADDR is set to register address corresponding to the Port_ShortEvent Counter for the desired port. R/W Write: 0 Read: Undefined. Access Description R/W This register contains the data to be written on an SRAM write access. performed during DP83856B initialization. 17 SRAM writes should only be www.national.com ...
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... Description R These bits are the Revision level of the device and are embedded into the DP83856B silicon. initial revisions. R These bits are a vendor specific code embedded in the DP83856B. Reads 0 for initial revision. R/W Write: 0 Read: Undefined. Access Description R Contains data corresponding to the SRAM location selected ...
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... For single Physical Layer Management register read accesses and single statistic read accesses to connected DP83850s, the read data appears in data register address A0h. When the DP83856B is instructed block statistics read from a connected DP83850, the block of 7 read values is placed in the registers A0h to ACh. The register’ ...
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A.C. and D.C. Specifications 5.1 D.C. Specifications Symbol Parameter V Minimum High Level Output Voltage OH V Maximum Low Level Output Voltage OL V Minimum High Level Input Voltage IH V Maximum Low Level Input Voltage IL I Input ...
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... T9 -CCS high to -CRDY high T11 -CCS low to -CRDY low T12 -CCS low to CPU Data valid T13 CPU Data hold from -CRDY low 5.2.3 MII Slave Timing (DP83856B receiving data on RDIO) T15 RDC -SDV RRDIR RDIO (slave) T14 RDC pulse width T15 ...
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... MII Master Timing (DP83856B sending data on RDIO) RDC -SDV RRDIR RDIO(mstr) T14 RDC pulse width T19 RDC falling edge to -SDV falling edge T20 RDC falling edge to RDIO valid T21 RDC falling edge to RDIO invalid T22 RRDIR rising edge to -SDV falling edge ...
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... T40 T41 -SOE high to -SCS high Notes: 1. All SRAM read cycles are Address controlled. 2. SRAM must have a read access time of 20ns or faster. 3. The DP83856B latches data prior to changing the SA[12:0] value. 4. The DP83856B latches data prior to terminating -SOE. T30 T33 T32 T31 ...
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SRAM Write Timing -SCS SR-W -SOE SA[12:0] SD[15:0] T42 -SCS low to SA[12:0] valid T43 SA[12:0] valid to SR-W low T44 SR-W width T45 SD[15:0] valid to SR-W high T46 SR-W high to SA[12:0] invalid T47 SR-W high to ...
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Test Mode Timing LC T48 T49 -TSTATE -TEST_EN -TEST_H_L Group 1 Outputs Group 2 Outputs T48 -TSTATE low to Group 1 Outputs Hi-Z T49 -TSTATE low to Group 2 Outputs Hi-Z T50 -TSTATE high to Group 1 Outputs driven ...
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... The DP83856B uses definition (1) by setting the upper limit on runts to 564 bits or 141 nibbles. Therefore if the packet activity is greater than 141 nibbles, the DP83856B does not log the activity as a runt. This opens a window for events which are not logged either as a runt or a good/fcs frame. ...
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... ID may be latched from Management Data (MD[3:0]). Depending on the actual device ID latched, the DP83856B may either not log the packet in the correct location or may not log the packet at all. To avoid the possibility of not counting a packet after random invalid management bus activity, use external logic to ensure that -M_DV is asserted only when TX_RDY is also asserted ...
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... English Tel: (+49) 0-180-532 78 32 National does not asseme any responsibility for use of anu circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time with notice, to change said circuitry or specifications. Order Number DP83856BVF NS Package Number VF132A 2. A critical component is any component of a life ...