dp83820 National Semiconductor Corporation, dp83820 Datasheet - Page 45

• Manufacturer Part Number: dp83820
• Description: 10/100/1000 Mb/s Pci Ethernet Network Interface Controller
• Manufacturer: National Semiconductor Corporation

4.0 Register Set
4.2.5 PCI Test Control Register
4.2.6 Interrupt Status Register
This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the
Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more
bits in this register are set to a “1”. The Interrupt Status Register reflects all current pending interrupts, regardless of the
state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.
31-16
12-11
bit
15
14
13
10
bit
31
30
29
28
27
9
8
7
6
5
4
3
2
1
0
RBIST_RX1FAIL
RBIST_RX0FAIL
RBIST_TX0FAIL
TXDESC3
TXDESC2
TXDESC1
TXDESC0
RBIST_HFFAIL
RBIST_RXFAIL
RBIST_DONE
EEBIST_FAIL
EELOAD_EN
RBIST_RST
EEBIST_EN
RBIST_EN
tag
tag
Offset: 000Ch
Offset: 0010h
(Continued)
Tag: PTSCR
Tag: ISR
Reserved
Tx Descriptor for Priority
Queue 3
Tx Descriptor for Priority
Queue 2
Tx Descriptor for Priority
Queue 1
Tx Descriptor for Priority
Queue 0
Reserved
Reserved
Reserved
SRAM BIST Reset
Reserved
SRAM BIST Enable
SRAM BIST Done
RX Status FIFO BIST Fail
RX Data FIFO BIST Fail
Reserved
TX Data FIFO BIST Fail
Hash Filter BIST Fail
RX Filter BIST Fail
Enable EEPROM Load
Enable EEPROM BIST
EE BIST Fail indication
description
description
Access: Read Write
Access: Read Only
Reserved
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated.
This event is signaled after a transmit descriptor with the INTR bit set in the
CMDSTS field has been updated.
Size: 32 bits
Size: 32 bits
Reserved
Reserved. Must be written as a 0.
Reserved
Setting this bit to 1 allows the SRAM BIST engine to be reset. R/W
Reserved
Setting this bit to 1 starts the SRAM BIST engine. R/W
This bit is set to 1 when the SRAM BIST completes each section. RO
This bit is set to 1 if the SRAM BIST detects a failure in RX Status
FIFO SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in RX Data FIFO
SRAM. This bit is cleared only by resetting the BIST. RO
Reserved
This bit is set to 1 if the SRAM BIST detects a failure in TX Data FIFO
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in the hash filter
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to 1 if the SRAM BIST detects a failure in the RX filter
SRAM. This bit is cleared only by resetting the BIST. RO
This bit is set to a 1 to manually initiate a load of configuration
information from EEPROM. A 1 is returned while the configuration
load from EEPROM is active. R/W
This bit is set to a 1 to initiate EEPROM BIST, which verifies the
EEPROM data and checksum without reloading configuration values
to the device. A 1 is returned while the EEPROM BIST is active. R/W
This bit is set to a 1 upon completion of the EEPROM BIST
(EEBIST_EN returns 0) if the BIST logic encountered an invalid
checksum. RO
45
usage
Hard Reset: 00000000h
Hard Reset: 00608000h
Soft Reset: 00000000h
Soft Reset: 00608000h
usage
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