dp83821 National Semiconductor Corporation, dp83821 Datasheet
dp83821
Related parts for dp83821
dp83821 Summary of contents
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... DP83821 is a single-chip 10/100/1000 Mb/s Ethernet Controller for the PCI bus targeted at high- performance adapter cards and mother boards. The DP83821 fully implements the V2.2 33 MHz, 32-bit PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU ...
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... AD22 200 PCIVDD 201 AD21 202 AD20 203 AD19 204 COREVSS 205 COREVDD 206 AD18 207 AD17 208 DP83821 Gigabit NIC Order Number DP83821VUW See NS Package Number NVUW208A 2 104 MD7 103 MD6 102 MD5 101 MD4/EEDO 100 VDDIO 99 VSSIO 98 MD3 97 MD2 96 ...
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... As a target, PAR is asserted during read data phases. I/O Parity Error: The DP83821 as a master or target will assert this signal low to indicate a parity error on any incoming data (except for special cycles bus master, it will monitor this signal on all write operations (except for special cycles) ...
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... PCI bus power during the D3 power management state. This pin pad has an internal weak pull down. I/O Clockrun: This signal is asserted low by DP83821 to indicate that a Clockrun Event has occurred. I PCI Bus VIO: This pin should be connected to the VIO pins of the PCI bus. It provides a direct connection to the ESDPLUS ring for biasing ...
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... During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s operation this clock is 2.5 MHz +/- 100 ppm. Receive PMA Clock 0: In TBI mode, this 62.5Mhz clock is used in conjunction with RXPMACLK1 to clock 10-bit TBI data into the DP83821. The rising edge of RXPMACLK0 clocks the odd-numbered bytes. O Gigabit Transmit Data: This is a group of 8 signals which are driven synchronous to GTXCLK ...
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... Transmit Error: This signal is synchronous to TXCLK and provides error indications and also is used for 1000 Mb/s half-duplex carrier extension and packet bursting functions. The DP83821 will only assert this signal in 1000 Mb/s mode of operation. TBI Transmit Data: In TBI mode, this is TXD9 of the 10-bit TBI Transmit data. ...
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... I Crystal/Oscillator Input: This pin is the primary clock reference input for the DP83821 IC and must be connected to a 25MHz 0.005% (50ppm) clock source. The DP83821 device supports either an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. ...
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... Pin Descriptions (Continued) Serial EEPROM Interface Symbol Pin No(s) Direction MA3/EEDI 108 MD4/EEDO 101 Note: DP83821 supports NMC93C46 for the eeprom interface device. JTAG Interface Symbol Pin No(s) Direction TCK 178 TDI 181 TDO 180 TMS 179 TRSTN 177 Supply Pins Symbol Pin No(s) ...
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... Description These pins must be tied to high through individual 1 Kohm resistors tied to Vdd (3.3 V) for proper operation of the DP83821 recommended these pins be tied low (0 V) for proper operation of the DP83821. 9 www.national.com ...
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... Functional Description DP83821 consists of a PCI bus interface, BIOS ROM and EEPROM interfaces, Receive and Transmit Data Buffer PCI Bus Interface 32 32 93C06 Serial EEPROM Figure 3-1 3.1 DP83821 The DP83821 device is an enhanced version of the NSC MacPhyter MAC/BIU (Media ...
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... REQ64N pin and determines the bus to be 32- (Continued) 3.2.1 Byte Ordering The DP83821 can be configured to order the bytes of data on the AD[31:0] bus to conform to Little Endian or Big Endian ordering through the use of the CFG:BEM bit. Byte ordering only affects bus mastered packet data transfers in 32-bit mode ...
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... PERRN (Continued) Figure 3-4 Target Read Operation Data at that time, the DP83821 will assert TRDYN. On the next clock the 32-bit double word will be latched in, and TRDYN will be forced HIGH for 1 cycle and then tri-stated. Note: Target write operations must be 32-bits wide. If FRAMEN is asserted beyond the assertion of IRDYN, the DP83821 will still latch the first double word as described above, but will also issue a Disconnect ...
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... FRAMEN will be forced HIGH (it will be tri-stated 1 cycle later). On the next clock edge that the device detects TRDYN asserted, it will force IRDYN HIGH. It, too, will be tri-stated 1 cycle later. This will conclude the write operation. The DP83821 will never force a wait state during a write operation. 13 www.national.com ...
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... FIFO is emptied and filled is controlled by the FIFO threshold values in the TXCFG register: FLTH (Tx Fill Threshold), and DRTH (Tx Drain Threshold). Additionally, once the DP83821 requests the bus, it will attempt to fill the FIFO as allowed by the MXDMA setting in the TXCFG register. 3.4.2 Transmit Priority Queueing The Tx Buffer Manager process also supports priority queueing of transmit packets ...
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... FIFO. Control and status registers in the DP83821 govern the operation of the MAC unit. The standard 802.3 Ethernet packet consists of the following fields: preamble, start of frame delimiter (SFD), destination address, source address, length, data, frame check sequence (FCS) and Extension (See Figure 3-8) ...
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... MDIO). Many of the signals are shared with the MII interface. One significant difference is the Transmit clock (GTXCLK) is supplied by the DP83821 instead of the Phy. The management interface (described later) is the same in both MII and GMII modes 3.8.3 Ten-Bit Interface (TBI) ...
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... EEPROM Interface The DP83821 supports the attachment of an external EEPROM. The EEPROM interface provides the ability for the DP83821 to read from and write data to an external serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a hardware reset. The DP83821 will " ...
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Functional Description RXFCSErrors RFC 1643, 802.3 LM RXMsdPktErrors RFC 1213, RFC 1643, 802.3 LM RXFAEErrors RFC 1643, 802.3 LM RXSymbolErrors 802.3 LM RXFrameTooLong RFC 1643, 802.3 LM RXIRLErrors 802.3 LM RXBadOpcodes 802.3 LM RXPauseFrames 802.3 LM TXOctetsOK RFC 1213, ...
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... RFC 1643, 802.3 LM TXSQEErrors RFC 1643 3.13 Buffer Management The buffer management scheme used on the DP83821 allows quick, simple and efficient use of the frame buffer memory. Frames are saved in similar formats for both transmit and receive. The buffer management scheme also uses ...
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... Set the data consumer of the descriptor to return ownership to the data producer of the descriptor. For transmit descriptors, the driver is the data producer, and the DP83821 is the data consumer. For receive descriptors, the DP83821 is the data producer, and the driver is the data consumer. ...
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... Table 3-5 Receive Bit Definitions description Set DP83821 when the receive was aborted. If RXO is set, then the receive was aborted due overrun. If RXO is clear, then a receive descriptor error occurred. SIZE will be set to the amount of data that was transferred to memory when the error was detected. ...
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Functional Description bit tag 31-22 21 UDPPKT UDP Packet 20 19 TCPPKT TCP Packet 18 17 IPPKT IP Packet 16 VPKT VLAN Packet 15-0 VTCI VLAN Tag Control Information bit tag 31-23 22 UDPERR UDP Checksum Error 21 UDPPKT ...
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... All descriptors will initially be owned by the producer of the data (the driver for transmit, the DP83821 for receive). The OWN bit is used by both driver and the DP83821 to (Continued) Figure 3-10 Single Descriptor Packets single descriptor / single fragment ...
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Functional Description Descriptors Organized in a Ring (Recommended Method) addr 10100 10140 3.13.2.4 Descriptor Lists Descriptors may also be organized in linked lists using the link field. The linked list may be terminated by either a NULL link field, ...
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... Without Priority Queueing, the device will draw packets from a single Descriptor list. Only one descriptor pointer is required. When the CR:TXEN bit is set to 1 (regardless of the current state), and the DP83821 transmitter is idle, then Figure 3-15 Transmit Architecture with Priority Queueing Transmit Descriptor ...
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Functional Description 3.13.3.1 Transmit State Machine The transmit state machine has the following states: txIdle txDescRefr txDescRead txFifoBlock txFragRead txDescWrite txAdvance The transmit state machine manipulates the following internal data spaces: TXDP CTDD TxDescCache descCnt fragPtr txFifoCnt txFifoAvail Inputs ...
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... NULL CR:TXEN && CTDD txDescRefr XferDone txAdvance XferDone txDescWrite 3.13.3.2 Transmit Data Flow without Priority Queueing In the DP83821 transmit architecture without Priority Queueing, packet transmission involves the following steps: 1. The device driver receives packets from an upper layer available DP83821 transmit allocated ...
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... When the RXEN bit is set the CR register (regardless of the current state), and the DP83821 receive state machine is idle, then DP83821 will read the contents of the descriptor (Continued) 3.13.3.3 Transmit Data Flow with Priority Queueing The transmit architecture with Priority Queueing is the same with a few minor differences: — ...
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Functional Description Figure 3-18 Receive Architecture with Priority Queueing Receive Descriptor List link link Q0 bufptr bufptr cmdsts cmdsts link link Q1 bufptr bufptr cmdsts cmdsts link link Q2 bufptr bufptr cmdsts cmdsts link link Q3 bufptr bufptr cmdsts ...
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Functional Description FifoReady (rxPktCnt > (rxPktBytes > rxDrainThreshold) ... in other words have a complete packet in the FIFO (regardless of size), or the number of bytes that we do have is greater than the ...
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... Receive Data Flow without Priority Queueing With a bus mastering architecture, some number of buffers and descriptors for received packets must be pre-allocated when the DP83821 is initialized. The number allocated will directly affect the system's tolerance to interrupt latency. The more buffers that you pre-allocate, the longer the ...
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Functional Description 3.13.5.2 Receive Data Flow with Priority Queueing With Priority Queueing still necessary to pre-allocate buffers and descriptors. Each priority queue must have a separate list of descriptors allocated. The receive data flow is similar to ...
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... Register Set 4.1 Configuration Registers The DP83821 implements a PCI version 2.2 configuration register space. This allows a PCI BIOS to "soft" configure the DP83821. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to their hardware reset state. For all unused registers, writes are ignored, and reads return 0. ...
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... Unused (reads return 0) Device Command bits (see below). Unused (reads return 0) Set the PCI BIOS to enable the DP83821 to do Fast Back-to-Back transfers (FBB transfers as a master is not implemented in the current revision). When set, DP83821 will generate SERRN when an address parity error is detected ...
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... CLS Cache Line Size DP83821 Bus Master Operations: Based on cache line size, the DP83821 will use the following PCI commands for bus mastered transfers: 0110 - Mem Read Single dword read transfers 1110 - Mem Read Line Read More than 1 dword but not across a cacheline boundary ...
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... Read Only. Set DP83821 for target 32-bit addressing. Loaded from EEPROM (location 05h, bit 3) at power-up and is reflected in the CFG:T64ADDR bit in operational register space. Must Read Only. Set DP83821 to indicate that DP83821 is capable of being mapped into memory space. Size: 32 bits ...
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... This is used by the PCI BIOS to enable accesses to boot ROM. This allows the DP83821 to share the address decode logic between the boot ROM and itself. The BIOS will copy the contents of the boot ROM to system RAM before executing it. Set to 1 enables the address decode for boot ROM disabling access to operational target registers ...
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... D1 Support 24-22 AUX_CURRENT 3 bit field for aux current requirement. 21 DSI Device Specific Initialization This bit is set indicate to the system that initialization of the DP83821 Size: 32 bits Hard Reset: 340b0100h Access: Read Write Soft Reset: unchanged usage The DP83821 desired setting for Max Latency. The DP83821 will initialize this field to 52d (13 usec) ...
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... When set to 1, this bit enables the assertion of the PME function on the PMEN pin. When 0, the PMEN pin is forced to be inactive. This value can be loaded from the EEPROM. unused (reads return 0) This 2 bit field is used both to determine the current power state of DP83821, and to set a new power state D3hot 39 www ...
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... Operational Registers The DP83821 provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations are ignored. Reads to reserved register locations return undefined values. When mapped to I/O space, a 256 byte window allows access to all the Operational Registers (00-FCh). When mapped into PCI memory space, a 4096 byte window is enabled ...
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... Command Register This register is used for issuing commands to the DP83821. These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. Setting control bits to 0 has no effect, therefore there is no need for Read/modify/writes to this register. ...
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Register Set (Continued) 4 TXR Transmit Reset 3 RXD Receiver Disable 2 RXE Receiver Enable 1 TXD Transmit Disable 0 TXE Transmit Enable 4.2.2 Configuration and Media Status Register This register allows configuration of a variety of device and ...
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... R/W This bit controls the assertion of SERR when a data parity error is detected while the DP83821 is acting as the bus master. When set, parity errors will not result in the assertion of SERR. When reset, parity errors will result in the assertion of SERR, indicating a system error. This bit should be set software if the driver can handle recovery from and reporting of data parity errors ...
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Register Set (Continued) 4.2.3 MII/EEPROM Access Register The MII/EEPROM Access Register provides an interface for software access to the serial management port of an external MII device or NMC9306 style EEPROM. The default values given assume that the MDIO ...
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Register Set (Continued) 4.2.4 EEPROM Map EEPROM Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh Registers for SOPAS[47:0] and PMATCH[47:0] can be accessed directly via the combination of the RFCR (offset 0048h) ...
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Register Set (Continued) 4.2.5 PCI Test Control Register Tag: PTSCR Offset: 000Ch bit tag 31-16 Reserved 15 Reserved 14 Reserved 13 RBIST_RST SRAM BIST Reset 12-11 Reserved 10 RBIST_EN SRAM BIST Enable 9 RBIST_DONE SRAM BIST Done 8 RBIST_RX1FAIL ...
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... This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits) when the ISR register is read. The DP83821 signaled a system error on the PCI bus. The DP83821 received a master abort generated as a result of target not responding. The DP83821 received a target abort on the PCI bus. ...
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Register Set (Continued) 4.2.7 Interrupt Mask Register This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting ...
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Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. Tag: IER Offset: 0018h bit tag description 31 Interrupt Enable 4.2.9 Interrupt Holdoff Register The Interrupt Holdoff Register prevents interrupt assertion ...
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... This register is reserved. It must always be read and written as 00000000h. 4.2.12 Transmit Configuration Register This register defines the Transmit Configuration for DP83821. It controls such functions as Loopback, Heartbeat, Auto Transmit Padding, programmable Interframe Gap, Fill & Drain Thresholds, and maximum DMA burst size. Tag: TXCFG ...
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Register Set (Continued) 15-8 FLTH Tx Fill Threshold 7-0 DRTH Tx Drain Threshold 4.2.13 General Purpose I/O Control Register This register allows configuration of the General Purpose I/O pins. Note that these pins are especially useful when interfacing to ...
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... This register is reserved and must always be read and written as 00000000h. 4.2.16 Receive Configuration Register This register is used to set the receive configuration for DP83821. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here Tag: RXCFG ...
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Register Set (Continued) 27 ALP Accept Long Packets 26 AIRL Accept In-Range Length Errored Packets 25-23 22-20 MXDMA Max DMA Burst Size per Rx DMA Burst 19-6 5-1 DRTH Rx Drain Threshold 0 4.2.17 Priority Queueing Control Register This ...
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Register Set (Continued) 3-2 RXPQ Receive Priority Queue Enable 1 TXFAIR Transmit Fairness Enable 0 TXPQEN Transmit Priority Queueing Enable This 2-bit field is used to enable Receive Priority Queueing. The number of priority queues is determined by the ...
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... Wake Command/Status Register The WCSR register is used to configure/control and monitor the DP83821 Wake On LAN logic. The Wake On LAN logic is used to monitor the incoming packet stream while in a low-power state, and provide a wake event to the system if the desired packet type, contents, or Link change are detected. ...
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... Pause Control/Status Register The PCR register is used to control and monitor the DP83821 Pause Frame reception and transmission. The Pause Frame reception Logic is used to accept 802.3x Pause Frames, extract the pause length value, and initiate a TX MAC pause interval of the specified number of slot times ...
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Register Set (Continued) 25-24 PS_STHI RX Stat FIFO Hi Threshold 23-22 PS_STLO RX Stat FIFO Lo Threshold 21-20 PS_FFHI RX Data FIFO Hi Threshold 19-18 PS_FFLO RX Data FIFO Lo Threshold 17 PS_TX Transmit Pause Frame 16 Reserved 15-0 ...
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... Register Set (Continued) 4.2.20 Receive Filter/Match Control Register The RFCR register is used to control and configure the DP83821 Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Tag: RFCR Offset: 0048h bit tag description 31 RFEN Rx Filter Enable ...
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Register Set (Continued) 9-0 RFADDR Receive Filter Extended Register Address 4.2.21 Receive Filter/Match Data Register The RFDR register is used for reading from and writing to the internal receive filter registers, the pattern buffer memory, and the hash table ...
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Register Set (Continued) 4.2.22 Receive Filter Logic The Receive Filter Logic supports a variety of techniques for qualifying incoming packets. The most basic filtering options include Accept All Broadcast, Accept All Multicast and Accept All Unicast packets. These options ...
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Register Set (Continued) Pattern 3 Word 3Fh Pattern 3 Word 0 Pattern 2 Word 3Fh Pattern 2 Word 0 Pattern 1 Word 3Fh Pattern 1 Word 0 Pattern 0 Word 3Fh Pattern 0 Word 1 Pattern 0 Word 0 ...
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Register Set (Continued) 4.2.22.3 Accept on Multicast or Unicast Hash Multicast and Unicast addresses may be further qualified by use of the receive filter hash functions. An internal 2048 bit (256 byte) RAM-based hash table is used to perform ...
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... FLASH memory is used) the external Boot ROM. All accesses must be 32-bits wide and aligned on 32-bit boundaries. Size: 32 bits Hard Reset: as defined Access: Read Only Soft Reset: unchanged usage unused (reads return 0) Silicon Revision for the DP83821. Rev B 0103h 63 www.national.com ...
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Register Set (Continued) 4.2.26 Management Information Base Control Register The MIBC register is used to control access to the statistics block and the warning bits and to control the collection of management information statistics. Tag: MIBC Offset: 005ch bit ...
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... All MIB counters are cleared to 0 when read. Due to cost and space limitations, the counter bit widths provided in the DP83821 MIB are less than the bit widths called for in the above specifications assumed that management agent software will maintain a set of fully compliant statistic values (" ...
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Register Set (Continued) 4.2.28 Transmit Descriptor Pointer 1 Register This register points to the Transmit Descriptor for Priority Queue 1. Tag: TXDP1 Offset: 00A0h bit tag description 31-3 TXDP1 Transmit Descriptor Pointer 1 2-0 4.2.29 Transmit Descriptor Pointer 2 ...
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Register Set (Continued) 4.2.31 Receive Descriptor Pointer 1 Register This register points to the Receive Descriptor for Priority Queue 1. Tag: RXDP1 Offset: 00B0h bit tag description 31-3 RXDP1 Receive Descriptor Pointer 1 2-0 4.2.32 Receive Descriptor Pointer 2 ...
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Register Set (Continued) 4.2.33 Receive Descriptor Pointer 3 Register This register points to the Receive Descriptor for Priority Queue 3 (highest priority). Tag: RXDP3 Offset: 00B8h bit tag description 31-3 RXDP3 Receive Descriptor Pointer 3 2-0 4.2.34 VLAN/IP Receive ...
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Register Set (Continued) 4.2.35 VLAN/IP Transmit Control Register This register allows enabling of the various VLAN tag handling features and IP checksum offload features. Tag: VTCR Offset: 00C0h bit tag description 31-4 3 PPCHK Per-Packet Checksum Generation 2 GCHK ...
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Register Set (Continued) 4.2.38 TBI Control Register This register is used to enable and/or restart TBI auto-negotiation also used to enable PCS loopback of TBI data. Tag: TBICR Offset: 00E0h bit tag 15 14 MR_LOOPBACK TBI PCS ...
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Register Set (Continued) 13-12 RF2, RF1 Remote Fault 11-9 8-7 PS2, PS1 Pause Capability Encoding PS1 indicates that the device is capable of providing symmetric 6 HALF_DUP Half Duplex 5 FULL_DUP Full Duplex 4-0 4.2.41 TBI Auto-Negotiation Link Partner ...
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Register Set (Continued) 4.2.42 TBI Auto-Negotiation Expansion Register This register is a read-only register indicating if a new base page from the link partner has been received and if the local device is next page able. Writes to this ...
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DC and AC Specifications Absolute Maximum Ratings Supply Voltage ( 3.3 V PCI signaling, 5.0 V tolerant DC Input Voltage ( Output Voltage (V ) OUT Storage Temperature Range (T ) STG Power Dissipation ...
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DC and AC Specifications 5.2 AC Specifications 5.2.1 PCI Clock Timing PCICLK Number PCICLK Low Time 5.2.1.1 PCICLK High Time 5.2.1.2 PCICLK Cycle Time 5.2.1.3 5.2.2 X1 Clock Timing X1 Number X1 Low Time 5.2.2.1 X1 High Time 5.2.2.2 ...
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... EE Disabled Note 1: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies. Note 2: Minimum access after reset is dependent on PCI clock frequency. Accesses to DP83821 during this period will be ignored. Note disabled for non power on reset. 5.2.4 Non Power On Reset ...
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DC and AC Specifications 5.2.5 POR PCI Inactive VDD T1 EESEL Number VDD stable to EE access 5.2.5.1 VDD indicates the digital supply (AUX power plane, except PCI bus power.) Guaranteed by design. 5.2.6 PCI Bus Cycles The following ...
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DC and AC Specifications PCI Configuration Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] Addr C/BEN[3: IDSEL T1 IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Configuration Write PCICLK T1 ...
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DC and AC Specifications PCI Bus Master Read PCICLK T3 T3 FRAMEN T4 T3 AD[31:0] Addr T3 T3 Cmd C/BEN[3:0] IRDYN TRDYN DEVSELN PAR PERRN PCI Bus Master Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] Cmd IRDYN ...
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DC and AC Specifications PCI Target Read PCICLK T2 T1 FRAMEN T1 T2 AD[31:0] A ddr C/BEN[3: IRDYN TRDYN DEVSELN T1 T2 PAR PERRN PCI Target Write PCICLK T1 T2 ...
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DC and AC Specifications PCI Bus Master Burst Read PCICLK T3 FRAMEN T4 T3 AD[31:0] Addr T3 T3 Cmd C/BEN[3:0] T3 IRDYN TRDYN DEVSELN PAR PERRN PCI Bus Master Burst Write PCICLK T3 FRAMEN T3 AD[31:0] Addr T3 C/BEN[3:0] ...
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DC and AC Specifications PCI Bus Arbitration REQN GNTN 5.2.7 RX MII/GMII Interface RXCLK RXDV RXER RXD Number RXDV/RXER/RXD to RXCLK Setup 5.2.7.1 Requirement RXDV/RXER/RXD to RXCLK Hold 5.2.7.2 Requirement (Continued ...
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DC and AC Specifications 5.2.8 RX TBI Interface RXPMA CLK0 RXPMA CLK1 RXD Number RXD[9:0] to RXPMACLK0 or RXPMACLK1 5.2.8.1 Setup Requirement RXD[9:0] to RXPMACLK0 or RXPMACLK1 5.2.8.2 Hold Requirement 5.2.9 TX MII Interface TXCLK TXEN TXD Number TXEN/TXD ...
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DC and AC Specifications 5.2.10 TX GMII/TBI Interface GTXCLK TXEN TXD TXER Number TXEN/TXER/TXD Output Delay from 5.2.10.1 GTXCLK 5.2.11 EEPROM Auto-Load EECLK EESEL EEDO EEDI Number EECLK Cycle Time 5.2.11.1 EECLK Delay from EESEL 5.2.11.2 EECLK Low to ...
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DC and AC Specifications 5.2.12 Boot PROM/FLASH T5 T16 MCSN MRDN T3 MA[15:0] MD[7:0] MWRN Number Data Valid to MRDN Invalid 5.2.12.1 Data Invalid from MRDN Invalid 5.2.12.2 Address Valid to MRDN 5.2.12.3 Address Invalid from MRDN Invalid 5.2.12.4 ...
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DC and AC Specifications 5.2.13 JTAG Timing TCK TDO (output) TCK TDI, TMS (input) TCK non-test inputs TCK non-test outputs Number TCK Period 5.2.13.1 TCK low/high time 5.2.13.2 TCK to TDO (Output) Delay Time 5.2.13.3 TDI, TMS (Input) to ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number DP83821VUW See NS Package Number NVUW208A 2. A critical component is any component of a life ...