dp8392a National Semiconductor Corporation, dp8392a Datasheet

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dp8392a

Manufacturer Part Number
dp8392a
Description
Coaxial Transceiver Interface
Manufacturer
National Semiconductor Corporation
Datasheet

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C 1995 National Semiconductor Corporation
DP8392A NS32492A Coaxial Transceiver Interface
General Description
The DP8392A Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
1 0 System Diagram
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
TL F 7405
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table of Contents
1 0 System Diagram
2 0 Block Diagram
3 0 Functional Description
3 1
3 2
3 3
3 4
4 0 Connection Diagram
5 0 Pin Descriptions
6 0 Absolute Maximum Ratings
7 0 Electrical Characteristics
8 0 Switching Characteristics
9 0 Timing and Load Diagram
10 0 Physical Dimensions
Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Integrates all transceiver electronics except signal
power isolation
Innovative design minimizes external component count
Jabber timer function integrated on chip
Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Precision circuitry implements receive mode collision
detection
Squelch circuitry at all inputs rejects noise
Designed
IEEE 802 3
Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Receiver and Squelch
Transmitter and Squelch
Collision and Heartbeat
Jabber Timer
for
rigorous
reliability
RRD-B30M105 Printed in U S A
requirements
TL F 7405 – 1
May 1988
of

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dp8392a Summary of contents

Page 1

... DP8392A NS32492A Coaxial Transceiver Interface General Description The DP8392A Coaxial Transceiver Interface (CTI coax- ial cable line driver receiver for Ethernet Thin Ethernet (Cheapernet) type local area networks The CTI is connect- ed between the coaxial cable and the Data Terminal Equip- ...

Page 2

... Ethernet Specifications for signal levels Controlled rise and fall times ( harmonic components The rise and fall times are matched to minimize jitter The drive current levels of the DP8392A meet the tighter recommended limits of IEEE 802 3 and are set by a built-in bandgap reference and an external 1% re- sistor An on chip isolation diode is provided to reduce the Transmitter’ ...

Page 3

Functional Description 3 3 COLLISION FUNCTIONS The collision circuitry consists of two buffers two 4-pole Bessel low pass filters (section comparator a heart- beat generator a 10 MHz oscillator and a differential line driver Two ...

Page 4

... Connection Diagram e Note pulse transformer L 100 mH Pulse Engineering (San Diego) Part No 64103 Valor Electronics (San Diego) Part No 1101 or equivalent Top View Order Number DP8392AN See NS Package Number N16A FIGURE 7405 – 5 ...

Page 5

... P C BOARD LAYOUT The DP8392A package is uniquely designed to ensure that the device meets the 1 million hour Mean Time Between Failure (MTBF) requirement of the IEEE 802 3 standard In order to fully utilize this heat dissipation design the three Description Collision Output Balanced differential line driver outputs from the collision detect ...

Page 6

Absolute Maximum Ratings Supply Voltage ( Package Power Rating (PC Board Mounted) Derate linearly at the rate Input Voltage Storage Temperature Lead Temp (Soldering 10 seconds) For actual ...

Page 7

Timing and Load Diagrams FIGURE 5 Receiver Timing FIGURE 6 Transmitter Timing FIGURE 7 Collision Timing FIGURE 8 Heartbeat Timing 7405 – 7405 – 7405 – ...

Page 8

Timing and Load Diagrams The 50 mH inductance is for testing purposes Pulse transformers with higher inductances are recommended (see Figure 4 ) (Continued) FIGURE 9 Jabber Timing Input jitter Output ...

Page 9

9 ...

Page 10

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Molded Dual-In-Line Package (N) Order Number DP8392AN NS Package Number N16A 2 A critical component is any component of a life ...

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