dp8390d National Semiconductor Corporation, dp8390d Datasheet - Page 44

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dp8390d

Manufacturer Part Number
dp8390d
Description
Nic Network Interface Controller
Manufacturer
National Semiconductor Corporation
Datasheet

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15 0 Switching Characteristics
Note 1 Cycles T1’ T2’ T3’ T4’ are only issued for the first transfer in a burst when 32-bit mode has been selected
Note 2 The rate of bus clock must be high enough to support transfers to from the FIFO at a rate greater than the serial network transfers from to the FIFO
Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention
Symbol
bcyc
bch
bcl
bcash
bcasl
aswo
bcadv
bcadz
ads
adh
Bus Clock Cycle Time
(Note 2)
Bus Clock High Time
Bus Clock Low Time
Bus Clock to Address Strobe High
Bus Clock to Address Strobe Low
Address Strobe Width Out
Bus Clock to Address Valid
Bus Clock to Address TRI-STATE
(Note 3)
Address Setup to ADS0 1 Low
Address Hold from ADS0 1 Low
Parameter
DMA Address Generation
(Continued)
44
bch
bcl
22 5
22 5
Min
bch
50
15
b
b
15
5
1000
Max
34
44
45
55
TL F 8582 – 81
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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