dp83220 National Semiconductor Corporation, dp83220 Datasheet - Page 2

• Manufacturer Part Number: dp83220
• Description: Cdl Twisted Pair Fddi Transceiver Device
• Manufacturer: National Semiconductor Corporation

1 0 Functional Description
The CDL Transceiver consists of nine major functional
blocks as shown in Figure 1 The Transmit section includes
the following the Delay Line the Delay Line Calibrator the
Media Format Logic and the Current Output Driver circuitry
with its bias circuitry The Delay Line accepts the NRZI en-
coded data from the PMRD
‘‘memory’’ of the bit that preceded the bit currently being
transmitted The Delay Line Calibrator allows the use of an
external resistor which governs the time calibration of the
delay line The Delay Line outputs the data via taps which
are tied to the Media Format Logic The encoding logic is
dependent on the state of the Media Select pin The encod-
ed data is routed to the Current Output Driver through the
TXO
The Receive section consists of the following a differential
input amplifier Signal Detect circuitry a Loopback Multi-
plexer and differential 100K output drivers for data and Sig-
nal Detect The Receive signal is input to the RXI
from the receive isolation transformer The input signal is
sensed by the Signal Detect circuit The input signal also
drives a differential input amplifier whose output is coupled
to the Loopback Mux logic The ‘sel’ input which is driven by
LBEN controls which data stream RXI
2 0 Pinout Summary
V
GND
RXV
RXGND
TXV
TXGND
EXTV
RXI
PMID
PMRD
TXO
SD
TXREF
DELREF
LBEN
MSEL
CDET
g
Signal
CC
output pins and transformer coupled to the media
g
g
CC
CC
g
CC
g
g
Pin No
13 26
14 22
25 24
15 16
20 21
4 27
3 28
5 11
7 10
g
2 1
9 8
23
12
19
17
18
6
pins and provides a short
g
or Loopback data
V
GND
Receive V
Receive GND
Transmit V
Transmit GND
External V
Receive Data Inputs
Physical Media Indicate Data
Physical Media Request Data
Transmit Data Outputs
Signal Detect Outputs
Transmit Amplitude Reference
Delay Line Calibration Reference
Loopback Enable
Media Select
Cable Detect Bar
CC
g
pins
Description
CC
CC
CC
2
is routed to the differential 100K Output Driver When in
Loopback mode the Signal Detect output driver is forced
true When receiving data from copper media the signal
detect circuit provides valid states to the Signal Detect out-
put driver depending on the amplitude of the incoming sig-
nal and also allows the PMID
Detect is the final gating function for data reception If no
media is detected the transceiver will generate a logic low
Signal Detect which will inhibit data reception by the PHY
1 1 SDDI OPERATION
The CDL allows full compatibility with the current SDDI
specification By allowing the MSEL pin to float which
forces the pin to V
tion is selected The appropriate transmit voltage amplitude
must also be set by selecting a value of 2 6 kX for the
TXREF resistor
Finally it is important to note that the CDL must be used in
conjunction with the Pulse Engineering 8 3 magnetics mod-
ule in order to conform to the current SDDI specification No
special terminations are required in connecting the Pulse
Engineering 8 3 module to the CDL (Refer to the typical
SDDI schematic Figure 9 )
CC
2 internally the SDDI mode of opera-
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Current In
ECL Out
ECL In
Current Out
ECL Out
Current Out
Current Out
CMOS In
3-Level Select
CMOS Schmitt Trigger In
g
outputs to switch Cable
Type