km68257c Samsung Semiconductor, Inc., km68257c Datasheet
km68257c
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km68257c Summary of contents
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... KM68257C/CL Document Title 32Kx8 Bit High Speed Static RAM(5V Operating), Evolutionary Pin out. Operated at Commercial Temperature Range. Revision History Rev No. History Rev. 0.0 Initial release with Preliminary. Rev. 1.0 Release to final Data Sheet. 1. Delete Preliminary Rev. 2.0 Update A.C parameters 2.1. Updated A.C parameters Items ...
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... The KM68257C is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG's advanced CMOS process and designed for high-speed circuit § ...
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... KM68257C/CL ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress ra ting only and func- tional operation of the device at these at these or any other conditions above those indicated in the operating sections of thi s specification is not implied ...
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... OHZ PRELIMINARY CMOS SRAM Value § À 3 1.5V See below , & OLZ OHZ +5.0V 480 DOUT 255 5pF* KM68257C/CL-20 Max Min Max - ...
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... WP1 WHZ (Address Controlled, CS=OE PRELIMINARY CMOS SRAM KM68257C/CL-20 Max Min Max Data Valid ...
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... KM68257C/CL TIMING WAVE FORM OF READ CYCLE(2) ADD CS OE Data Out Icc Vcc I SB Current NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... KM68257C/CL TIMING WAVE FORM OF WRITE CYCLE(2) ADD CS WE High-Z Data In Data Out TIMING WAVE FORM OF WRITE CYCLE(3) ADD CS WE High-Z Data In High-Z Data Out (OE=Low Fixed CW( AS(4) WP1(2) t WHZ(6) (CS=Controlled CW(3) t AS(4) t WP( WHZ( PRELIMINARY CMOS SRAM ...
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... KM68257C/CL NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the ear- liest transition CS going high or WE going high ...
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... KM68257C/CL PACKAGE DIMENSIONS 28-DIP-300 #28 7.01 0.20 0.276 0.008 #1 0. 0.025 28-SOJ-300 #28 8.51 0.12 0.335 0.005 #1 0.43 0.017 0. 0.0375 34.69 MAX 1.366 34.29 0.20 1.350 0.008 0.46 0.10 0.018 0.004 2.54 1.27 0.10 0.100 0.050 0.004 18.82 MAX 0.741 18.41 0.12 0.725 0.005 +0.10 -0.05 +0.004 +0.10 0.71 -0.002 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY CMOS SRAM Units : Inches (millimeters) 0.25 0.010 #15 #14 0~15 ¡ É ...
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... KM68257C/CL PACKAGE DIMENSIONS PACKAGE DIMENSIONS 28-TSOP1-0813.4F +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.55 #14 0.0217 0.25 TYP 0.010 0~8 ¡ É 0.45 ~0.75 0.018 ~0.030 13.40 0.20 0.528 0.008 #28 #15 11.80 0.10 +0.10 0.465 0.15 0.004 -0.05 +0.004 0.006 -0.002 0. 0.020 - 10 PRELIMINARY CMOS SRAM Units : Inches (millimeters) 0.425 ( ) 0.017 1.00 0.05 0.10 MIN 0.039 0.002 0.004 1.20 MAX 0.047 Rev 3.0 ...