lm4549a National Semiconductor Corporation, lm4549a Datasheet - Page 12

• Manufacturer Part Number: lm4549a
• Description: Ac ?97 Rev 2.1 Multi-channel Audio Codec With Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

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LNLVL_OUT_R
LNLVL_OUT_L
SDATA_OUT
Pin Descriptions
SDATA_IN
XTL_OUT
BIT_CLK
XTL_IN
SYNC
Name
Name
Pin
10
2
3
5
6
8
Pin
39
41
I / O
I / O
I/O
O
O
I
I
I
O
O
(Continued)
Functional Description
Left Stereo Channel Output
This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal
from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_L amplitude can be
muted (along with LNLVL_OUT_R) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps
Right Stereo Channel Output
This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal
from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_R amplitude can be
muted (along with LNLVL_OUT_L) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps
24.576 MHz crystal or oscillator input
To complete the oscillator circuit use a fundamental mode crystal operating in parallel
resonance and connect a 1MΩ resistor across pins 2 and 3. Choose the load capacitors
( Figure 2 , C1, C2 ) to suit the crystal (e.g. C1 = C2 = 33 pF for a crystal designed for a 20 pF
load. Assumes that each ’Input + trace’ capacitance = 7 pF)
This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at
standard logic levels (V
This pin is only used when the codec is in Primary mode. It may be left open (NC) for any
Secondary mode.
24.576 MHz crystal output
Used with XTAL_IN to configure a crystal oscillator.
When the codec is used with an external oscillator this pin should be left open (NC).
When the codec is configured in a Secondary mode this pin is not used and may be left open
(NC).
Input to codec
This is the input for AC Link Output Frames from an AC ’97 Digital Audio Controller to the
LM4549A codec. These frames can contain both control data and DAC PCM audio data. This
input is sampled by the LM4549A on the falling edge of BIT_CLK.
AC Link clock
An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC
Link. The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal
input (XTL_IN).
This pin is an INPUT when the codec is configured in any of the Secondary Codec modes
and would normally use the AC Link clock generated by a Primary Codec.
Output from codec
This is the output for AC Link Input Frames from the LM4549A codec to an AC ’97 Digital
Audio Controller. These frames can contain both codec status data and PCM audio data from
the ADCs. The LM4549A clocks data from this output on the rising edge of BIT_CLK.
AC Link frame marker and Warm Reset
This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of
BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25%
(16/256). SYNC is sampled on the rising edge of BIT_CLK and the codec takes the first
positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC
pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored.
SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm
Reset is used to clear a power down state on the codec AC Link interface.
DIGITAL I/O AND CLOCKING
ANALOG I/O (Continued)
IH
, V
IL
12
).
Functional Description