adv611 Analog Devices, Inc., adv611 Datasheet - Page 17

• Manufacturer Part Number: adv611
• Description: Closed Circuit Tv Digital Video Codec
• Manufacturer: Analog Devices, Inc.

MIN Cr Value Register
Indirect (Read Only) Register Index 0x0B1
The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
[31:0]
MAX Cr Value Register
Indirect (Read Only) Register Index 0x0B2
The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data. The
Host reads these values through the Host Interface.
[15:0]
[31:0]
Compressed Field Size [HI]
Indirect (Read Only) Register Index 0x83
[15:0]
Compressed Field Size [LO]
Indirect (Read Only) Register Index 0xB4
[3:0]
Bin Width and Reciprocal Bin Width Registers
Indirect (Read/Write) Register Index 0x0100-0x0153
The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and
MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes these
values through the Host Interface.
These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values as
indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, un-
signed, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined
at reset).
[15:0]
[15:0]
REV. 0
Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset)
Reserved (always read zero)
Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset)
Reserved (always read zero)
The DWORD Count registers hold the count of double (32-bit) words contained in the previously encoded field. This
count is useful for bit rate control algorithms that use a servo loop, which is locked to the expected number of double words
in the field. The registers are double buffered to ensure that the count remains constant while the next field's count accumu-
lates. Contains bits [19:4] of the DWORD count, reset is 0.
Contains bits [3:0] of the DWORD count, reset is 0. For more information, see the DWORD Count 16 MSB Register
description.
Bin Width Values, BW[15:0]
Reciprocal Bin Width Values, RBW[15:0]
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ADV611/ADV612