adv601 Analog Devices, Inc., adv601 Datasheet - Page 25

• Manufacturer Part Number: adv601
• Description: Low Cost Multiformat Video Codec
• Manufacturer: Analog Devices, Inc.

Host Interface
The ADV601 host interface is a high performance interface that
passes all command and real-time compressed video data be-
tween the host and codec. A 512 position by 32-bit wide, bidi-
rectional FIFO buffer passes compressed video data to and from
the host. The host interface is capable of burst transfer rates of
up to 132 million bytes per second (4 33 MHz). For host inter-
face pins descriptions, see the Pin Function Descriptions section.
For host interface timing information, see the Host Interface Timing
section.
DSP Interface
The DSP Interface is used to interface with an external DSP.
During encode, the DSP provides the ADV601 with Bin Width
calculation support (in applications where the host processor is
not providing Bin Width support). When the host provides Bin
Width calculation support, the DSP is not required. During
decode, the DSP is not needed. This interface is capable of
glueless connection with all of Analog Devices DSP serial ports.
The DSP interface passes the following information (in encode
only):
• Wavelet statistics calculated by the ADV601 output to the DSP
• Compression ratio output to the DSP
• Quantizer control information (i.e., Bin Width and Reciprocal
Figure 11 shows how to connect and ADV601 with a DSP.
Other figures that describe ADV601-to-DSP connections in-
clude Figures 15 and 16.
Figure 11. ADV601-to-ADSP-2105 (DSP) Serial Interface
Connections
ADV601 Serial Transfer Overview
The video statistics that the ADV601 calculates and sends to the
DSP for quantizer control calculations are as follows:
• Minimum pixel value per field per component
• Maximum pixel value per field per component
• Sum of pixel values per field per component
• Sum of squares of pixel values per Mallat block per component
• Compression Ratio (programmed by the host) per field
The ADV601 video codec can transmit video field statistics and
receive bin width values through its serial port when connected
to a DSP (an ADSP-21xx family DSP whose SPORT is set for
continuous Rx/Tx normal framing mode). This DSP-compatible
serial port has six pins: RXD, TXD, TCLK, TF, RF and DIRQ.
For DSP Interface pins descriptions, see Pin Function Descriptions.
REV. 0
Bin Width factors) input from the DSP
(SERIAL PORT)
ADSP-21xx
SCLK0
RFS0
TFS0
IRQ2
RD0
TD0
RF
RXDATA
TF
TXDATA
TCLK
DIRQ
(SERIAL INTERFACE)
ADV601
–25–
ADV601 Serial Transfer Process
On a field by field basis, the ADV601 transfers video statistics to
the DSP and then receives bin widths from the DSP. The tim-
ing of the data flow appears in Figure 41. The steps for the data
flow are as follows:
1. The ADV601 asserts DIRQ to alert the DSP that video sta-
2. The ADV601 transfers the statistics packet of fifty-two 16-bit
3. The DSP calculates bin width and reciprocal bin width val-
4. The DSP transfers the bin width and reciprocal bin width
5. The ADV601 de-asserts DIRQ after receiving the DSP’s bin
ADV601 Serial Transfer Implications
This serial I/O process between the ADV601 and the DSP con-
tinues for all fields of video. Some important implications that
stem from this process are as follows:
• Because the ADV601 asserts DIRQ near the beginning of
• Because failures in serial I/O to the DSP are possible, the
• Because failures in serial I/O from the DSP are possible, the
each video field, the signal can be useful for synchronizing
system wide operations that need to key on the beginning of
each video field.
DSP software times out if the video statistics packet does not
arrive within a specific time window and returns a default set
of bin width values to the ADV601.
ADV601 uses the bin width values from the previous field if
the DSP does not return new bin with values within a specific
time window.
tistics are ready for the first field.
words on the TXD pin using a pulse on TF to indicate the
beginning, most-significant-bit first, of each word.
The video statistics transfer for the first field occurs during
the first part of the next field. The address order of register
transfer is as follows: 0x06 (Compression Ratio), 0x80-0xA9
(Sum of Squares [0-41]), 0xAA (Sum of Luma), 0xAB (Sum
of Cb), 0xAC (Sum of Cr), 0xAD (Min Luma), 0xAE (Max
Luma), 0xAF (Min Cb), 0xB0 (Max Cb), 0xB1 (Min Cr),
and 0xB2 (Max Cr).
ues for each Mallat block, using the video statistics.
packet of eighty-four 16-bit words on the ADV601’s RXD
pin using a pulse on the ADV601’s RF to indicate the begin-
ning, most-significant-bit first, of each word.
The bin width and reciprocal bin width transfer for the first
field occurs before the end of the next field. The address
order of register transfer is as follows: 0x100 (Reciprocal Bin
Width 0), 0x101 (Bin Width 0), . . . , 0x152 (Reciprocal Bin
Width 41), 0x153 (Bin Width 41).
width and reciprocal bin width packet and keeps DIRQ de-
asserted until the video statistics packet for the next field is
ready for transfer.
ADV601