enc28j60 Microchip Technology Inc., enc28j60 Datasheet
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enc28j60 Summary of contents
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... Microchip Technology Inc. Stand-Alone Ethernet Controller with SPI Interface Preliminary ENC28J60 Data Sheet DS39662B ...
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... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...
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... NC SCK RESET 10 V SSRX 11 TPIN- 12 TPIN+ 13 RBIAS 14 28-pin QFN NC ENC28J60 SCK RESET 7 V SSRX Reserved pin; always leave disconnected. Preliminary LEDA 26 LEDB 25 V DDOSC 24 OSC2 23 OSC1 22 V ...
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... ENC28J60 Table of Contents 1.0 Overview ...................................................................................................................................................................................... 3 2.0 External Connections ................................................................................................................................................................... 5 3.0 Memory Organization ................................................................................................................................................................. 11 4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 25 5.0 Ethernet Overview ...................................................................................................................................................................... 31 6.0 Initialization................................................................................................................................................................................. 33 7.0 Transmitting and Receiving Packets .......................................................................................................................................... 39 8.0 Receive Filters............................................................................................................................................................................ 47 9.0 Duplex Mode Configuration and Negotiation.............................................................................................................................. 53 10.0 Flow Control ............................................................................................................................................................................... 55 11.0 Reset .......................................................................................................................................................................................... 59 12.0 Interrupts .................................................................................................................................................................................... 63 13.0 Direct Memory Access Controller ............................................................................................................................................... 71 14.0 Power-Down ............................................................................................................................................................................... 73 15.0 Built-in Self-Test Controller ........................................................................................................................................................ 75 16.0 Electrical Characteristics ............................................................................................................................................................ 79 17.0 Packaging Information................................................................................................................................................................ 83 Index ...
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... LED link and network activity indication. A simple block diagram of the ENC28J60 is shown in Figure 1-1. A typical application circuit using the device is shown in Figure 1-2. With the ENC28J60, two pulse transformers and a few passive components are all that is required to connect a microcontroller to an Ethernet network. ...
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... ENC28J60 FIGURE 1-2: TYPICAL ENC28J60-BASED INTERFACE MCU CS I/O SI SDO SO SDI SCK SCK INT INT X TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number Pin Pin Name SPDIP, Type QFN SOIC, SSOP CAP CLKOUT 3 27 INT SCK ...
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... EXTERNAL CONNECTIONS 2.1 Oscillator The ENC28J60 is designed to operate at 25 MHz with a crystal connected to the OSC1 and OSC2 pins. The ENC28J60 design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer specifications. A typical oscillator circuit is shown in Figure 2-1 ...
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... When the OST expires, the CLKOUT pin will begin out- putting its default frequency of 6.25 MHz (main clock divided by 4). At any future time that the ENC28J60 is reset by software or the RESET pin, the CLKOUT func- tion will not be altered (ECOCON will not change ...
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... Magnetics, Termination and Other External Components To complete the Ethernet interface, the ENC28J60 requires several standard components to be installed externally. These components should be connected as shown in Figure 2-4. The internal analog circuitry in the PHY module requires that an external 2. resistor be attached from RBIAS to ground. The resistor influences the TPOUT+/- signal amplitude ...
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... ENC28J60 will detect how the LED is connected and begin driving the LED to the default state configured by the PHLCON register. If the LED polarity is changed while the ENC28J60 is operating, the new polarity will not be detected until the next system Reset occurs. LEDB is unique in that the connection of the LED is automatically read on Reset and determines how to ini- tialize the PHCON1 ...
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... Stretchable LED events will only be displayed while they are occurring bit 0 Reserved: Write as ‘0’ © 2006 Microchip Technology Inc. R/W-1 R/W-0 R/W-1 r LACFG3 LACFG2 R/W-0 R/W-0 R/W-0 LBCFG0 LFRQ1 LFRQ0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared LSTRCH MSTRCH NSTRCH Preliminary ENC28J60 R/W-0 R/W-0 LACFG1 LACFG0 bit 8 R/W-1 R/W-x STRCH r bit Bit is unknown DS39662B-page 9 ...
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... ENC28J60 NOTES: DS39662B-page 10 Preliminary © 2006 Microchip Technology Inc. ...
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... MEMORY ORGANIZATION All memory in the ENC28J60 is implemented as static RAM. There are three types of memory in the ENC28J60: • Control Registers • Ethernet Buffer • PHY Registers The Control registers’ memory contains the registers that are used for configuration, control and status retrieval of the ENC28J60 ...
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... Control registers for the ENC28J60 are generically grouped as ETH, MAC and MII registers. Register names starting with “E” belong to the ETH group. Similarly, registers names starting with “MA” belong to the MAC group and registers prefixed with “ ...
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... TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY Register Name Bit 7 Bit 6 EIE INTIE PKTIE EIR — PKTIF ESTAT INT BUFER ECON2 AUTOINC PKTDEC ECON1 TXRST RXRST ERDPTL Read Pointer Low Byte ERDPT<7:0>) ERDPTH — — EWRPTL Write Pointer Low Byte (EWRPT<7:0>) EWRPTH — ...
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... ENC28J60 TABLE 3-2: ENC28J60 CONTROL REGISTER SUMMARY (CONTINUED) Register Name Bit 7 Bit 6 EPMCSL Pattern Match Checksum Low Byte (EPMCS<7:0>) EPMCSH Pattern Match Checksum High Byte (EPMCS<15:0>) EPMOL Pattern Match Offset Low Byte (EPMO<7:0>) EPMOH — — ERXFCON UCEN ANDOR EPKTCNT Ethernet Packet Count MACON1 — ...
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... ECON1 REGISTER The ECON1 register, shown in Register 3-1, is used to control the main functions of the ENC28J60. Receive enable, transmit request, DMA control and bank select bits can all be found in ECON1. REGISTER 3-1: ECON1: ETHERNET CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 TXRST RXRST DMAST bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
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... ENC28J60 3.1.2 ECON2 REGISTER The ECON2 register, shown in Register 3-2, is used to control other main functions of the ENC28J60. REGISTER 3-2: ECON2: ETHERNET CONTROL REGISTER 2 (1) R/W-1 R/W-0 R/W-0 AUTOINC PKTDEC PWRSV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit ...
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... All writes it does will not be subject to any wrapping conditions. See Section 13.0 “Direct Memory Access Controller” for more information. Preliminary ENC28J60 “Transmitting Packets” for more and write ...
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... ENC28J60 FIGURE 3-2: ETHERNET BUFFER ORGANIZATION Transmit Buffer Start (ETXSTH:ETXSTL) Buffer Write Pointer (EWRPTH:EWRPTL) Transmit Buffer End (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) Buffer Read Pointer (ERDPTH:ERDPTL) Receive Buffer End (ERXNDH:ERXNDL) DS39662B-page 18 0000h Transmit Buffer Data AAh (WBM AAh) Transmit Buffer Receive Buffer ...
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... When the MIISCAN operation is in progress, the host controller must not attempt to write to MIWRH or start an MIIRD operation. The MIISCAN operation can be cancelled by clearing the MICMD.MIISCAN bit and then polling the MISTAT.BUSY bit. New operations may be started after the BUSY bit is cleared. Preliminary ENC28J60 DS39662B-page 19 ...
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... ENC28J60 DS39662B-page 20 Preliminary © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R-0 R-0 — r NVALID U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 R/W-0 R/W-0 MIISCAN MIIRD bit Bit is unknown R-0 R-0 SCAN BUSY bit Bit is unknown DS39662B-page 21 ...
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... ENC28J60 3.3.4 PHSTAT REGISTERS The PHSTAT1 and PHSTAT2 registers contain read- only bits that show the current status of the PHY module’s operations, particularly the conditions of the communications link to the rest of the network. The PHSTAT1 register (Register 3-5) contains the LLSTAT bit; it clears and latches low if the physical layer link has gone down since the last read of the register ...
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... PHY has not detected any jabbering transmissions since PHSTAT1 was last read bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. R-1 R-1 U-0 PFDPX PHDPX — U-0 U-0 R/LL-0 — — LLSTAT U = Unimplemented bit, read as ‘0’ Bit latches low Preliminary ENC28J60 U-0 U-0 — — bit 8 R/LH-0 U-0 JBSTAT — bit Bit latches high DS39662B-page 23 ...
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... ENC28J60 REGISTER 3-6: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2 U-0 U-0 R-0 — — TXSTAT bit 15 U-0 U-0 R-0 — — PLRITY bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 TXSTAT: PHY Transmit Status bit 1 = PHY is transmitting data 0 = PHY is not transmitting data ...
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... Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the ENC28J60 on the SO line, on the falling edge of SCK. The CS pin must be held low while any operation is performed and returned high when finished ...
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... Write and bit field instructions are also followed by one or more bytes of data. A total of seven instructions are implemented on the ENC28J60. Table 4-1 shows the command codes for all operations. Byte 0 Opcode Argument ...
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... MII register interface (see Section 3.3.1 “Reading PHY Registers” for more information). The RCR command is started by pulling the CS pin low. The RCR opcode is then sent to the ENC28J60, followed by a 5-bit register address (A4 through A0). The 5-bit address identifies any of the 32 control FIGURE 4-3: ...
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... Section 3.3.2 “Writing PHY Registers” for more information). The WCR command is started by pulling the CS pin low. The WCR opcode is then sent to the ENC28J60, followed by a 5-bit address (A4 through A0). The 5-bit address identifies any of the 32 control registers in the current bank. After the WCR command and address are sent, actual data that written is sent, MSb first ...
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... ENC28J60, followed by the 5-bit constant 1Ah. After the WBM command and constant are sent, the data to be stored in the memory pointed to by EWRPT should be shifted out MSb first to the ENC28J60. After 8 data bits are received, the Write Pointer will automatically increment if AUTOINC is set. The host controller can ...
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... ENC28J60 4.2.7 SYSTEM RESET COMMAND The System Reset Command (SRC) allows the host controller to issue a System Soft Reset command. Unlike other SPI commands, the SRC is only a single- byte command and does not operate on any register. FIGURE 4-7: SYSTEM RESET COMMAND SEQUENCE SCK ...
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... ETHERNET OVERVIEW Before discussing the use of the ENC28J60 as an Ethernet interface, it may be helpful to review the structure of a typical data frame. Users requiring more information should refer to IEEE Standard 802.3 which is the basis for the Ethernet protocol. 5.1 Packet Format Normal IEEE 802.3 compliant Ethernet frames are between 64 and 1518 bytes long ...
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... The data field is a variable length field anywhere from 0 to 1500 bytes. Larger data packets will violate Ethernet standards and will be dropped by most Ethernet nodes. The ENC28J60, however, is capable of transmitting and receiving larger packets when the Huge Frame Enable bit is set (MACON3.HFRMEN = 1). ...
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... INITIALIZATION Before the ENC28J60 can be used to transmit and receive packets, certain device settings must be initial- ized. Depending on the application, some configuration options may need to be changed. Normally, these tasks may be accomplished once after Reset and do not need to be changed thereafter. 6.1 Receive Buffer ...
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... ENC28J60 6.5 MAC Initialization Settings Several of the MAC registers require configuration during initialization. This only needs to be done once; the order of programming is unimportant. 1. Set the MARXEN bit in MACON1 to enable the MAC to receive frames. If using full duplex, most applications should also set TXPAUS and RXPAUS to allow IEEE defined flow control to function ...
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... MAC will operate in Full-Duplex mode. PDPXMD bit must also be set MAC will operate in Half-Duplex mode. PDPXMD bit must also be clear. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TXCRCEN PHDREN HFRMEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 R/W-0 R/W-0 FRMLNEN FULDPX bit Bit is unknown DS39662B-page 35 ...
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... ENC28J60 REGISTER 6-3: MACON4: MAC CONTROL REGISTER 4 U-0 R/W-0 R/W-0 — DEFER BPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting to transmit (use this setting for 802 ...
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... The settings for LED operation are discussed in Section 2.6 “LED Configuration”. The PHLCON register is shown in Register 2-2 (page 9). R/W-0 R/W-0 R/W JABBER R/W-0 R/W-0 R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 R/W-0 R/W-0 r HDLDIS bit 8 R/W-0 R/W bit Bit is unknown DS39662B-page 37 ...
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... ENC28J60 NOTES: DS39662B-page 38 Preliminary © 2006 Microchip Technology Inc. ...
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... TRANSMITTING AND RECEIVING PACKETS 7.1 Transmitting Packets The MAC inside the ENC28J60 will automatically gener- ate the preamble and start-of-frame delimiter fields when transmitting. Additionally, the MAC can generate any padding (if needed) and the CRC if configured to do so. The host controller must generate and write all other frame fields into the buffer memory for transmission ...
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... Start the transmission process by setting ECON1.TXRTS DMA operation was in progress while the TXRTS bit was set, the ENC28J60 will wait until the DMA opera- tion is complete before attempting to transmit the packet. This possible delay is required because the DS39662B-page 40 Memory ...
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... The attached CRC in the packet did not match the internally generated CRC. Number of collisions the current packet incurred during transmission attempts. It applies to successfully transmitted packets and as such, will not show the possible maximum count of 16 collisions. Total bytes in frame not counting collided bytes. Preliminary ENC28J60 DS39662B-page 41 ...
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... ENC28J60 TABLE 7-2: SUMMARY OF REGISTERS USED FOR PACKET TRANSMISSION Register Bit 7 Bit 6 Name EIE INTIE PKTIE EIR — PKTIF ESTAT INT BUFER ECON1 TXRST RXRST ETXSTL TX Start Low Byte (ETXST<7:0>) ETXSTH — — ETXNDL TX End Low Byte (ETXND<7:0>) ETXNDH — — MACON1 — ...
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... Receive Status Vector rsv[23:16] status[23:16] rsv[30:24] status[31:24] data[1] data[2] Packet Data: Destination Address, Source Address, Type/Length, Data, Padding, CRC crc[31:24] data[m-3] crc[23:16] data[m-2] crc[15:8] data[m-1] crc[7:0] data[m] Byte Skipped to Ensure Even Buffer Address Start of the Next Packet Preliminary ENC28J60 DS39662B-page 43 ...
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... ENC28J60 TABLE 7-3: RECEIVE STATUS VECTORS Bit Field 31 Zero 30 Receive VLAN Type Detected 29 Receive Unknown Opcode 28 Receive Pause Control Frame 27 Receive Control Frame 26 Dribble Nibble 25 Receive Broadcast Packet 24 Receive Multicast Packet 23 Received Ok 22 Length Out of Range 21 Length Check Error 20 CRC Error 19 Reserved ...
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... Receive Buffer Read Pointer, ERXRDPT. The ENC28J60 will always write up to, but not includ- ing, the memory pointed to by the Receive Buffer Read Pointer. If the ENC28J60 ever attempts to overwrite the Receive Buffer Read Pointer location, the packet in progress will be aborted, the EIR ...
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... ENC28J60 TABLE 7-4: SUMMARY OF REGISTERS USED FOR PACKET RECEPTION Register Bit 7 Bit 6 Name EIE INTIE PKTIE EIR — PKTIF ESTAT INT BUFER ECON2 AUTOINC PKTDEC ECON1 TXRST RXRST ERXSTL RX Start Low Byte (ERXST<7:0>) ERXSTH — — ERXNDL RX End Low Byte (ERXND<7:0>) ERXNDH — ...
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... RECEIVE FILTERS To minimize the processing requirements of the host controller, the ENC28J60 incorporates several different receive filters which can automatically reject packets which are not needed. Six different types of packet filters are implemented: • Unicast • Pattern Match • Magic Packet™ ...
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... ENC28J60 REGISTER 8-1: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER R/W-1 R/W-0 R/W-1 UCEN ANDOR CRCEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 UCEN: Unicast Filter Enable bit When ANDOR = Packets not having a destination address matching the local MAC address will be discarded ...
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... Yes Unicast packet? No Yes Yes Pattern matches? No Yes Yes Magic Packet for us? No Yes Yes Hash table bit set? No Yes Yes Multicast destination? No Yes Yes Broadcast destination? No CRCEN set CRC valid? Reject Packet Accept Packet Preliminary ENC28J60 Yes No Yes DS39662B-page 49 ...
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... ENC28J60 FIGURE 8-2: RECEIVE FILTERING USING AND LOGIC Packet Detected on Wire ANDOR = 1 (AND) DS39662B-page 50 Yes No Unicast UCEN set? packet? No Yes Yes Pattern No PMEN set? matches? No Yes Yes No Magic Packet MPEN set? for us? No Yes Yes No Hash table HTEN set? bit set? No Yes ...
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... Another example of a pattern matching filter is illustrated in Figure 8-3. SA Type/Length 64-byte Window used for Pattern Match Preliminary ENC28J60 calculates checksums (see Data FCS DS39662B-page 51 ...
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... ENC28J60 8.3 Magic Packet™ Filter The Magic Packet filter checks the destination address and data fields of all incoming packets. If the destination address matches the MAADR registers and the data field holds a valid Magic Packet pattern someplace FIGURE 8-4: SAMPLE MAGIC PACKET™ FORMAT ...
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... Half-Duplex Operation The ENC28J60 operates in Half-Duplex mode when MACON3.FULDPX = 0 and PHCON1.PDPXMD = 0. If only one of these two bits is set, the ENC28J60 will indeterminate state and not function correctly. Since switching between Full and Half-Duplex modes may result in this indeterminate state, the host control- ler should not transmit any packets (maintain ECON1 ...
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... ENC28J60 NOTES: DS39662B-page 54 Preliminary © 2006 Microchip Technology Inc. ...
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... Ethernet medium. Any connected nodes will see the transmission and either not transmit anything, waiting for the ENC28J60’s transmission to end, or will attempt to transmit and immediately cause a collision. Because a collision will always occur, no nodes on the network will be able to communicate with each other and no new packets will arrive ...
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... ENC28J60 To enable flow control on the ENC28J60 in Full-Duplex mode, the host controller must set the TXPAUS and RXPAUS bits in the MACON1 register. Then, at any time that the receiver buffer is running out of space, the host controller should turn flow control on by writing the value 02h to the EFLOCON register ...
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... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used. © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 DMAST CSUMEN TXRTS RXEN — r TXPAUS RXPAUS — — — FULDPXS Preliminary ENC28J60 Reset Bit 1 Bit 0 Values on page BSEL1 BSEL0 13 PASSALL MARXEN 14 14 FCEN1 FCEN0 DS39662B-page 57 ...
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... ENC28J60 NOTES: DS39662B-page 58 Preliminary © 2006 Microchip Technology Inc. ...
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... RESET The ENC28J60 differentiates between various kinds of Reset: • Power-on Reset (POR) • System Reset • Transmit Only Reset • Receive Only Reset • Miscellaneous MAC and PHY Subsystem Resets A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 11-1. FIGURE 11-1: ON-CHIP RESET CIRCUIT ...
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... When the RESET pin is held high, the ENC28J60 will operate normally. The ENC28J60 can also be reset via the SPI using the System Reset Command. See Section 4.0 “Serial Peripheral Interface (SPI)”. The RESET pin will not be driven low by any internal Resets, including a System Reset Command via the SPI interface ...
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... PRST and wait for it to become clear before using the PHY. U-0 R/W-0 R/W-0 — PPWRSV r U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 U-0 R/W-0 — PDPXMD bit 8 U-0 U-0 — — bit Bit is unknown DS39662B-page 61 ...
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... ENC28J60 NOTES: DS39662B-page 62 Preliminary © 2006 Microchip Technology Inc. ...
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... INTERRUPTS The ENC28J60 has multiple interrupt sources and an interrupt output pin to signal the occurrence of events to the host controller. The interrupt pin is designed for use by a host controller that is capable of detecting fall- ing edges. Interrupts are managed with two registers. The EIE ...
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... ENC28J60 12.1 INT Interrupt Enable (INTIE) The INT Interrupt Enable bit (INTIE global enable bit which allows the following interrupts to drive the INT pin: • Receive Error Interrupt (RXERIF) • Transmit Error Interrupt (TXERIF) • Transmit Interrupt (TXIF) • Link Change Interrupt (LINKIF) • ...
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... RXERIE: Receive Error Interrupt Enable bit 1 = Enable receive error interrupt 0 = Disable receive error interrupt © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 LINKIE TXIE Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 R/W-0 R/W-0 TXERIE RXERIE bit Bit is unknown DS39662B-page 65 ...
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... ENC28J60 REGISTER 12-3: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER U-0 R-0 R/C-0 — PKTIF DMAIF bit 7 Legend Readable bit C = Clearable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 PKTIF: Receive Packet Pending Interrupt Flag bit 1 = Receive buffer contains one or more unprocessed packets; cleared when PKTDEC is set ...
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... R/W-0 R-0 R-0 PLNKIE Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x R R/SC-0 R-0 R/SC-0 PLNKIF r PGIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ENC28J60 R-0 R bit 8 R/W-0 R/W-0 PGEIE r bit Bit is unknown R-x R bit 8 R-x R bit Bit is unknown DS39662B-page 67 ...
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... EIE.INTIE = 1), an interrupt is generated by driving the INT pin low. If the receive error interrupt is not enabled (EIE.RXERIE = 0 or EIE.INTIE = 0), the host controller may poll the ENC28J60 for the RXERIF and take appropriate action. Normally, upon the receive error condition, the host ...
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... INT pin low. If the link change interrupt is not enabled (EIE.LINKIE = 0, EIE.INTIE = 0, PHIE.PLNKIE = 0 or PHIE.PGEIE = 0), the host controller may poll the ENC28J60 for the PHIR.PLNKIF bit and take appropriate action. The LINKIF bit is read-only. Because reading from PHY registers requires non-negligible time, the host controller may instead set PHIE ...
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... Register 8-1 for available Section 12.2.1 “Setup Steps for Waking Magic Packet” shows the steps necessary in configur- ing the ENC28J60 to send an interrupt signal to the host controller upon the reception of a Magic packet. DS39662B-page 70 12.2.1 SETUP STEPS FOR WAKING MAGIC PACKET 1 ...
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... Start the DMA copy by setting ECON1.DMAST transmit operation is in progress (TXRTS set) while the DMAST bit is set, the ENC28J60 will wait until the transmit operation is complete before attempting to do the DMA copy. This possible delay is required because the DMA and transmission engine share the same memory access port ...
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... ENC28J60 13.2 Checksum Calculations The checksum calculation logic treats the source data as a series of 16-bit big-endian integers. If the source range contains an odd number of bytes, a padding byte of 00h is effectively added to the end of the series for purposes of calculating the checksum. The calculated checksum is the 16-bit one’s complement of the one’s complement sum of all 16-bit integers ...
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... POWER-DOWN The ENC28J60 may be commanded to power-down via the SPI interface. When powered down, it will no longer be able to transmit and receive any packets. To maximize power savings: 1. Turn off packet reception ECON1.RXEN. 2. Wait for any in-progress packets to finish being received by polling ESTAT.RXBUSY. This bit should be clear before proceeding ...
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... ENC28J60 NOTES: DS39662B-page 74 Preliminary © 2006 Microchip Technology Inc. ...
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... BUILT-IN SELF-TEST CONTROLLER The ENC28J60 features a Built-in Self-Test (BIST) module which is designed to confirm proper operation of each bit in the 8-Kbyte memory buffer. Although it is primarily useful for testing during manufacturing, it remains present and available for diagnostic purposes by the user. The controller writes to all locations in the buffer memory and requires several pieces of hardware shared by normal Ethernet operations ...
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... ENC28J60 15.1 Using the BIST When the BIST controller is started, it will fill the entire buffer with the data generated for the current test configuration and it will also calculate a checksum of the data written. When the BIST is complete, the EBSTCS registers will be updated with the checksum. ...
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... Bit 3 Bit 2 DMAST CSUMEN TXRTS RXEN — RX End High Byte (ERXND<12:8>) — DMA Start High Byte (EDMAST<12:8>) — DMA End High Byte (EDMAND<12:8>) PSV0 PSEL TMSEL1 TMSEL0 Preliminary ENC28J60 Reset Bit 1 Bit 0 Values on page BSEL1 BSEL0 ...
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... ENC28J60 NOTES: DS39662B-page 78 Preliminary © 2006 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. , and V , with respect to V ................................................ -0.3V to 3.6V DDTX SS ........................................................................... -0.3V to 6.0V SS ...............................-0. ............................................................................... -0.3V to 5.0V SS Preliminary ENC28J60 0°C to +70°C (Commercial) + 0.3V DD DS39662B-page 79 ...
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... ENC28J60 16.1 DC Characteristics: ENC28J60 (Industrial and Commercial) DC CHARACTERISTICS Param. Sym Characteristic No. D001 V Supply Voltage DD D002 V V Power-on Reset POR DD Voltage D003 S V Rise Rate to ensure VDD DD internal Power-on Reset signal V Input High Voltage IH D004 SCK, CS, SI, RESET D005 OSC1 V Input Low Voltage ...
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... TABLE 16-1: AC CHARACTERISTICS: ENC28J60 (INDUSTRIAL AND COMMERCIAL) AC CHARACTERISTICS TABLE 16-2: OSCILLATOR TIMING CHARACTERISTICS Param. Sym Characteristic No. F Clock In Frequency OSC T Clock In Period OSC T Duty Cycle DUTY (external clock input) f Clock Tolerance TABLE 16-3: RESET AC CHARACTERISTICS Param. Sym Characteristic No. trl RESET Pin High Time (between Reset events) ...
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... ENC28J60 FIGURE 16-1: SPI INPUT TIMING T CSS CS SCK MSb In SI 1/F SCK SO FIGURE 16-2: SPI OUTPUT TIMING CS SCK MSb Out 1/F SCK LSb In SI TABLE 16-6: SPI INTERFACE AC CHARACTERISTICS Param. Sym Characteristic No. F Clock Frequency SCK Setup Time CSS Hold Time ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. Example ENC28J60-I/SP 0610017 Example ENC28J60-I/SO 0610017 Example ENC28J60 e -C/SS 3 0610017 Example ENC28J60 e -I/ML 3 0610017 Preliminary ENC28J60 DS39662B-page 83 ...
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... ENC28J60 17.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width ...
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... A1 .004 .008 .012 E .394 .407 .420 E1 .288 .295 .299 D .695 .704 .712 h .010 .020 .029 L .016 .033 .050 .009 .011 .013 B .014 .017 .020 Preliminary ENC28J60 A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. ...
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... ENC28J60 28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP) Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. ...
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... BSC A .031 .035 .039 A1 .000 .001 .002 A3 .008 REF E .232 .236 .240 E2 .153 .167 .169 D .232 .236 .240 D2 .153 .167 .169 .009 .011 .013 L .018 .022 .024 K .008 – – Preliminary ENC28J60 MILLIMETERS* MIN NOM MAX 28 0.65 BSC 0.80 0.90 1.00 0.00 0.02 0.05 0.20 REF 5.90 6.00 6.10 3.89 4.24 4.29 5.90 6.00 6.10 3.89 4.24 4.29 0.23 0.28 0.33 0.45 0.55 0.65 0.20 – ...
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... ENC28J60 NOTES: DS39662B-page 88 Preliminary © 2006 Microchip Technology Inc. ...
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... Absolute Maximum Ratings ........................................ 79 AC Characteristics ...................................................... 81 CLKOUT Pin AC ......................................................... 81 DC Characteristics ...................................................... 80 Oscillator Timing ......................................................... 81 Requirements for External Magnetics......................... 81 Reset AC..................................................................... 81 SPI Interface AC ......................................................... 82 ENC28J60 Block Diagram .................................................... 3 EREVID Register ................................................................ 22 Errata .................................................................................... 2 Ethernet Buffer .................................................................... 17 Organization (Diagram)............................................... 18 Ethernet Module Transmitting and Receiving Data Receive Packet Layout ....................................... 43 Transmit Packet Layout ...................................... 40 © ...
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... System Reset Command Sequence........................... 30 Write Buffer Memory Command Sequence ................ 29 Write Control Register Command Sequence.............. 28 Transmit Buffer ................................................................... 17 Transmit Only Reset ........................................................... 60 Transmitting Packets .......................................................... 39 Associated Registers .................................................. 42 Status Vectors ............................................................ 41 Typical ENC28J60-Based Interface...................................... 4 U Unicast Filter....................................................................... 51 W WWW, On-Line Support ....................................................... 2 Preliminary © 2006 Microchip Technology Inc. ...
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... Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com Preliminary ENC28J60 should contact their distributor, DS39662B-page 91 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: ENC28J60 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... Microchip Technology Inc. Examples: a) ENC28J60-I/SP: Industrial temperature, SPDIP package. b) ENC28J60-I/SO: Industrial temperature, SOIC package. c) ENC28J60T-I/SO: Tape and Reel, Industrial temperature, SOIC package. d) ENC28J60-C/SS: Commercial temperature, SSOP package. e) ENC28J60T-C/SS: Tape and Reel, Comercial temperature, SSOP package. f) ENC28J60-I/ML: Industrial temperature, QFN package. Preliminary ENC28J60 . DS39662B-page 93 ...
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... Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Preliminary © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...