at83c26 ATMEL Corporation, at83c26 Datasheet - Page 43

• Manufacturer Part Number: at83c26
• Description: Multiple Smart Card Reader Interface With Power Management
• Manufacturer: ATMEL Corporation

Table 23. SC1_STATUS (Status Byte for SC1)
7511D–SCR–02/07
Bit Number
7
6
5
4
3
2
1
0
Bit Number
CC81
7
7
Bit Mnemonic
Bit Mnemonic
CC41
CARDRST1
CARDCK1
CKSTOP1
CARDC81
CARDC41
CARDIO1
6
IODIS1
CC81
0
Reset value = 0x 0110 0000
CARDIN1
Description
This bit should not be set.
Card I/O isolation
Set this bit to drive the CIO1, CC41, CC81 pins according to CARDIO1, CARDC41, CARDC81
respectively.
Clear this bit to drive the CIO1, CC41 and CC81 pins connected to inputs according to IOSEL[3/0] bits.
CARD Clock Stop
Set this bit to stop CCLK1 according to CARDCK1. This can be used to set asynchronous cards in power-
down mode (GSM) or to drive CCLK1 by software.
Clear this bit to have CCLK1 running according to CKS1. This can be used to activate asynchronous cards.
Note:
Card Reset
Set this bit to enter a reset sequence according to ART1 bit value.
Clear this bit to drive a low level on the CRST1 pin.
Card C8
Set this bit to drive the CC81 pin High with the on-chip pull-up (according to IODIS1 bit value). The pin can
then be an input (read in SC1_STATUS register).
Clear this bit to drive a low level on the CC81 pin (according to IODIS1 bit value).
Card C4
Set this bit to drive the CC41 pin High with the on-chip pull-up (according to IODIS1 bit value). The pin can
then be an input (read in SC1_STATUS register).
Clear this bit to drive a low level on the CC41 pin (according to IODIS1 bit value).
Card Clock
Set this bit to set a high level on the CCLK1 pin (according to CKSTOP1 bit value).
Clear this bit to drive a low level on the CCLK1 pin.
Card I/O
Set this bit to drive the CIO1 pin High with the on-chip pull-up (according to IODIS1 bit value). The pin can
then be an input (read in SC1_STATUS register).
Clear this bit to drive a low level on the CIO1 pin (according to IODIS1 bit value).
5
Description
Card CC8
This bit provides the actual level on the CC8 pin when read.
When this bit is changed a special logic ensures that no glitch occurs on the CCLK1 pin and
actual configuration changes can be delayed by half a period to two periods of CCLK1.
VCARD_OK1
4
3
X
VCARD_INT1
2
CRST1
1
AT83C26
CIO1
0
43