mc33991dwr2 Freescale Semiconductor, Inc, mc33991dwr2 Datasheet - Page 13

• Manufacturer Part Number: mc33991dwr2
• Description: Gauge Driver Integrated Circuit
• Manufacturer: Freescale Semiconductor, Inc

DATA INPUT
the SCLK clock. The SCLK clock pulses exactly 16 times only
inside the transmission windows (CS in a logic [0] state). By
the time the CS signal goes to logic [1] again, the contents of
the Input Shift register are transferred to the appropriate
internal register, according to the address contained in bits
15-13. The minimum time CS should be kept high depends
on the internal clock speed. That data is specified in the SPI
Interface Timing Table. It must be long enough so the internal
micro controller, via the 16-bit SPI protocol described and
specified below. The device is controlled by the
microprocessor and reports back status information via the
SPI. This section provides a detailed description of all
registers accessible via serial interface. The various registers
control the behavior of this device.
MSB (D15) and ending with the LSB (D0). Multiple
messages can be transmitted in succession to accommodate
Analog Integrated Circuit Device Data
Freescale Semiconductor
The input Shift register captures data at the falling edge of
The 33991device is capable of interfacing directly with a
A message is transmitted by the master beginning with the
SCLK
SCLK
CS
SO
SI
SO
CS
C S B
S C L K
SI
S O
S I
N O T E S :
O u tp u t s h ift re g is te r is
lo a d e d h e r e
C S B
S C L K
S O
S I
N O T E S :
D 1 5
1 .
2 .
3 .
4 .
O D 1 5
D 1 5
1 .
O D 1 5
S O is tri- s ta te d w h e n C S B is lo g ic 1 .
D 1 5 , D 1 4 , D 1 3 , ..., a n d D 0 re fe r to th e fir s t 1 6 b its o f d a ta in to th e G D IC .
D 1 5 * , D 1 4 * , D 1 3 * , ... , a n d D 0 * re fe r to th e m o s t re c e n t e n try o f p ro g r a m d a ta in to th e G D IC .
O D 1 5 , O D 1 4 , O D 1 3 , ..., a n d O D 0 r e fe r to th e firs t 1 6 b its o f fa u lt a n d s ta tu s d a ta o u t o f th e G D IC .
D 1 4
S O is tr i-s ta te d w h e n C S B is lo g ic 1 .
O D 1 4
D 1 4
O D 1 4
D 1 3
O D 1 3
TIMING DESCRIPTIONS AND DIAGRAMS
D 1 3
CS is logic 1.
O D 1 3
Figure 6. Multiple 16-Bit Word SPI Communication
Figure 5. Single 16-Bit Word SPI Communication
CS is logic 1.
D 1 2
O D 1 2
COMMUNICATION MEMORY MAPS
D 1 1
O D 1 1
D 2
O D 2
D 1 0
O D 1 0
D 1
O D 1
D 9
O D 9
D 0
O D 0
D 8
O D 8
D 1 5 *
D 1 5
D 7
clock is able to capture the data from the input Shift register
and transfer it to the internal registers.
DATA OUTPUT
logic [0], the contents of the Status Word register are
transferred to the Output Shift register. The first 16 bits
clocked out are the status bits. If data continues to clock in
before the CS transitions to a logic [1], the device to shift out
the data previously clocked in FIFO after the CS first
transitioned to logic [0].
those applications where daisy chaining is desirable, or to
confirm transmitted data, as long as the messages are all
multiples of 16 bits. Data is transferred through daisy chained
devices, illustrated in Figure 5. If an attempt is made to latch
in a message smaller than 16 bits wide, it is ignored.
control the state of the four H-bridge outputs. The registers
are addressed via D15-D13 of the incoming SPI word, in
Table 2.
O D 7
33991.
D 1 4 *
At the first rising edge of the SCLK clock, with the CS at
The 33991 uses six registers to configure the device and
D 1 4
D 6
O D 6
D 1 3 *
D 1 3
D 5
O D 5
33991.
D 4
O D 4
33991.
TIMING DESCRIPTIONS AND DIAGRAMS
D 3
O D 3
D 2 *
D 2
COMMUNICATION MEMORY MAPS
D 2
O D 2
D 1 *
D 1
D 1
O D 1
In te r n a l re g is te r s a re
D 0 *
D 0
D 0
lo a d e d s o m e tim e
a fte r th is e d g e
O D 0
33991
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