adm6999g Infineon Technologies Corporation, adm6999g Datasheet - Page 32

• Manufacturer Part Number: adm6999g
• Description: 8 Port 10/100 Mb/s + Gigabit Single Chip Ethernet Switch Controller
• Manufacturer: Infineon Technologies Corporation

Table 8
Register Short Name
VLAN_MTR_14
VLAN_MTR_15
PBTCR_P01
PBTCR_P23
PBTCR_P45
PBTCR_P67
TBTCR
PVID11_4_CR_P01
PVID11_4_CR_P23
PVID11_4_CR_P45
PVID11_4_CR_P67
PVID11_4_VLAN_CR
The register is addressed wordwise.
Table 9
Mode
read/write
read
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Data Sheet
Registers Overview (cont’d)
Register Access Types
Symbol Description HW
rw
r
ro
rv
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
Register Long Name
VLAN Mapping Table Register 14
VLAN Mapping Table Register 15
Port Buffer Threshold Control Reg. P0, P1
Port Buffer Threshold Control Reg. P2, P3
Port Buffer Threshold Control Reg. P4, P5
Port Buffer Threshold Control Reg. P6, P7
Total Buffer Threshold Control Register
Port0, 1 PVID bit11~4 Configuration Register
Port2, 3 PVID bit11~4 Configuration Register
Port4, 5 PVID bit 11~4 Configuration Register
Port6, 7 PVID bit 11~4 Configuration Register
P8 PVID bit 11~4/VLAN Group Shift Bits Conf.
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latches high signal at high level, clear
on read
Latches high signal at low-level, clear
on read
Latches high signal at high level,
register cleared with written mask
Latches high signal at low-level,
register cleared on read
Differentiates the input signal (low-
>high) register cleared on read
Differentiates the input signal (high-
>low) register cleared on read
Differentiates the input signal (high-
>low) register cleared with written mask
Differentiates the input signal (low-
>high) register cleared with written
mask
32
Description SW
Register is readable and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
Offset Address
21
22
23
24
25
26
27
28
29
2A
2B
2C
H
H
H
H
H
H
H
H
H
H
H
H
Rev 1.31, 2005-11-25
ADM6999G/GX
Page Number
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Descriptions