mc92300 Freescale Semiconductor, Inc, mc92300 Datasheet

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mc92300

Manufacturer Part Number
mc92300
Description
Viterbi Decoder For Digital Tv
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
VITERBI Decoder for Digital TV
Digital-TV applications according to the EBU defined DVB transmission standard for
satellite and cable Set-Top systems.
Viterbi Decoder - Capability Specification
MOTOROLA, INC. 1997
This document contains information on a new product.
Specifications and information herein are subject to change without notice.
Operates at max. 50MBits/s output rate to work with all present DVB channels
Implements K=7, (171
with a survivor depth of 96
Code rate and synchronization control programmable via I
Automatic rate selection and signal quality output (qval)
Full/empty flag generation of input FIFO for system monitoring of VDCLK/BITCLK
ratio
Simplified system design with internal PLL for the generation of output BITCLK
from the incoming VDCLK for all depuncturing modes
Available in a 128QFP package
This product preview describes a high performance device, a Viterbi Decoder, for
VDCLK
VC1[2:0]
VC2[2:0]
SYMCLK
RESET_N
8
,133
Synchronizer
8
) Viterbi decoder for rates 1/2, 2/3, 3/4, 5/6 and 7/8
VFF
Figure 1. Viterbi Decoder Block Diagram
VLCK
SR
QVAL
APLL
FIFO
VTSTI[1:0]
2
2
Depuncturing
C standard serial bus
VEF
SCL DSA SDA
I
Interface
2
C
7
Viterbi
Core
Current Information@www.mot.com/ADC
MC92300CG
Ordering Information
Device
BIT-
CLK
VO
MC92300
RESET_N
VC0,VC1[2:0]
VDCLK
VTSTI[1:0]
SDA
DSA[6:0]
SCL
SYMCLK
DTVVIT
BITCLK
SR[2:0]
Package
128QFP
VLCK
VEF
VFF
VO
5/28/97

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mc92300 Summary of contents

Page 1

... APLL VLCK 2 SR VTSTI[1:0] QVAL Figure 1. Viterbi Decoder Block Diagram Current Information@www.mot.com/ADC MC92300 DTVVIT BITCLK RESET_N VC0,VC1[2:0] VDCLK SYMCLK VTSTI[1:0] SR[2:0] SDA DSA[6:0] SCL Ordering Information Device Package MC92300CG Viterbi VO Core BIT- CLK Interface 7 SCL DSA SDA VO VLCK VFF VEF 128QFP 5/28/97 ...

Page 2

... The internal registers of the VITERBI are accessible 2 C interface. After reset, default values are prepro- In order to allow a simple system design, a Analogue are generated for a given [MHz] R [MHz] for rates s o 1/2 2/3 38.3 28.3 37.7 42.4 47.2 49.5 20.5 20.5 27.3 30.7 34.2 35.9 1 4/3 o The MC92300 is used in satellite receiver implementa- The MC92300 is available in a 128-pin Plastic Quad 3/4 5/6 7/8 3/2 5/3 7/4 MC92300 Rev.1.3 ...

Page 3

... VEF - FIFO Empty Flag SR[2:0] - Selected Rate VO - Viterbi Decoder Output VC0,VC1[2:0] - Soft Decision Input 2 SDA - Data Bus of I DSA[6:0] - Slave Address of I SCL - Clock Line of I TESTSEL, FREF, TESTOUT, VCOCTL - APLL pins MC92300 Rev.1 ...

Page 4

... RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET:http://mot-sps.com/sps/General/sales.html are registered trademarks of Motorola, Inc. Motorola, Inc Equal JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC92300 ...

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