dp8473 National Semiconductor Corporation, dp8473 Datasheet
dp8473
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dp8473 Summary of contents
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... DP8473 Floppy Disk Controller PLUS-2 General Description This controller is a full featured floppy disk controller that is software compatible with the mPD765A but also includes many additional hardware and software enhancements These enhancements include additional logic specifically re- quired for an IBM PC PC-XT PC-AT This controller incorporates a precision analog data separa- ...
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... IBM formats as well as Sony 3 5 (ISO) formats and other enhancements Block Diagram Note 1 The MTR2 MTR3 DR2 and DR3 are not available on the 48 pin DIP (DP8473N J) versions Note 2 See Figure 4 for filter description Note 3 Total transistor count is 29 700 (approx) ...
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... Pin Descriptions DP8473 DP8473 Symbol PCC DIP – – 19 Address lines from the microprocessor This determines which registers the microprocessor is accessing as shown in Table IV in the Register Description Section Don’t care during DMA transfers Active low input to enable the RD and WR inputs Not required during DMA transfers ...
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... Pin Descriptions (Continued) DP8473 DP8473 Symbol PCC DIP MTR0 8 6 This is an active low motor enable line for drive 0 which is controlled by the Drive Control register This is a high drive open drain output MTR1 7 5 This is an active low motor enable line for drive 1 Similar to MTR0 ...
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... DP8473 and many of the enhancements provided Re- fer to Figure 1 765A COMPATIBLE MICRO-ENGINE The core of the DP8473 is a mPD765A compatible micro- coded engine This engine consists of a sequencer pro- gram ROM and disk misc registers This core is clocked by either a 4 MHz 4 8 MHz or 8 MHz clock selected in the Data ...
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... Filter c) 250 500 kb s and Figure 4 shows several possible filter configurations For a filter to cover all data rates ( Figure 4c ) the DP8473 has filter always connected and other capacitor filter com- ponents for the other data rates are switched in parallel to ...
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... Mb s 500 kb s 300 kb s 250 kb s PLL DIAGNOSTIC MODES In addition the DP8473 has two diagnostic modes to enable filter optimization 1) enabling the Charge Pump output sig- nal onto the PUMP PREN pin and 2) providing external C R control of the Read Gate signal to the data separator Both ...
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... AN-505 Floppy Disk Data Separator Design Guide for the DP8473) WRITE PRECOMPENSATION The DP8473 incorporates a single fixed 3-bit shift register This shift register outputs are tapped and multiplexed onto the write data output The taps are selected by a standard ...
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... D0 Drive 0 Seeking Same as above for drive 0 DATA REGISTER (Read Write) This is the location through which all commands data and status flow between the CPU and the DP8473 During the Command Phase the mP loads the controller’s commands into this register based on the Status Register Request for ...
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Register Description (Continued) TABLE VI Data Rate and Precompensation Programming Values DRVTYP D1 D0 Pin Normal values when PUMP ...
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Result Phase Status Registers D5 Seek End Seek or Recalibrate Command completed by the Controller (Used during Sense Interrupt com- mand ) D4 Equipment Check After a Recalibrate Command Track 0 signal failed to occur (Used during Sense Inter- rupt ...
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Result Phase Status Registers TABLE VIII Summary of FDC Registers Bits 7 6 Register DCR (W) MTR3 MTR2 Enable Enable MSR (R) Request Data for Direction Master Data 7 Data 6 DRR ( DKR (R) ...
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Processor Software Interface both be set before a byte can be read from the Data Regis- ter during the Result Phase If there is information to be transferred during the Execution Phase there are three methods that can be used ...
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Command Description Table READ DELETED DATA Command Phase MT MFM IPS DR1 DR0 Track Number Drive Head Number Sector Number Number of Bytes per Sector End of Track Sector ...
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Command Description Table SCAN HIGH OR EQUAL Command Phase MT MFM IPS DR1 DR0 Track Number Drive Head Number Sector Number Number of Bytes per Sector End of Track ...
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Command Description READ DATA The Read Data op-code is written to the data register fol- lowed by 8 bytes as specified in the Command Description Table After the last byte is written the controller starts looking for the correct sector ...
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Command Description (Continued) Data Mark is read the sector is read normally If a Regular Data Mark is found and the SK bit is set the sector is not read bit 6 of ST2 (Control Mark) is set and the ...
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Command Description (Continued) Notes e FE Data pattern of FE Clock pattern Data pattern of FC Clock pattern Data pattern of FB Clock pattern Data pattern of F8 ...
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... Since the DP8473’s head load signal is now the soft- ware controlled Motor lines in the Drive Control Register these timers only provide some delay from the initiation of a ...
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Command Description (Continued) SENSE DRIVE STATUS This two byte command obtains the status of a disk drive Status Register 3 is returned in the result phase and con- tains the drive status This command does not generate an interrupt MODE ...
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Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( ...
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... Filter pin and measuring the ratio of the charge pump current over the input current VCO P Note 8 The DP8473 is guaranteed to correctly decode a single shifted clock pulse at the end of a long series of non-shifted preamble bits as long as the single shifted pulse is shifted less than the amount specified Table II ...
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AC Electrical Characteristics MICROPROCESSOR READ TIMING Symbol Parameter t Address Valid prior to Read Strobe AR t Address Hold from Read Strobe RA t Read Strobe Width RR t Read Strobe and Chip Select to Data Valid RD t Address ...
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AC Electrical Characteristics OSC2 CLOCK AND RESET TIMING Symbol Parameter t Clock High Time H t Clock Low Time L t Reset Pulse Width RW DMA TIMING (Note 9) Symbol Parameter t End of DRQ from DAK AQ t DAK ...
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AC Electrical Characteristics DRIVE WRITE TIMING Symbol Parameter t Write Data Pulse Width WD t Head Select Setup to Write Gate Assertion HDS t Head Select Hold from Write Gate HDH Note 11 Whenever WGATE is asserted the WDATA line ...
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AC Test Conditions (Notes 11 12 13) Input Pulse Levels GND to 3V Input Rise and Fall Times Input and Output Reference Levels TRI-STATE Reference Levels Active High Active Low e Note 11 C 100 pF includes jig and scope ...
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... Physical Dimensions inches (millimeters) Plastic Dual-In-Line Package (N) Order Number DP8473N NS Package Number N48A 27 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Leaded Chip Carrier (V) Order Number DP8473V NS Package Number V52A 2 A critical component is any component of a life ...