m66220sp Mitsumi Electronics, Corp., m66220sp Datasheet

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m66220sp

Manufacturer Part Number
m66220sp
Description
256 X 8-bit Mail-box
Manufacturer
Mitsumi Electronics, Corp.
Datasheet
1.M66220SP.pdf (11 pages)
DESCRIPTION
The M66220 is a mail box that incorporates a complete CMOS shared
memory cell of 256 8-bit configuration using high-performance silicon
gate CMOS process technology, and is equipped with two access
ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations from/to shared memory
individually. This product also incorporates a port adjustment
arbitration function in address contention from both ports.
FEATURES
• Memory configuration of 256
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Completely static operation
• Built-in port arbitration function
• Low power dissipation CMOS design
• 5V single power supply
• Not Ready output pin is provided (open drain output)
• TTL direct-coupled I/O
• 3-state output for I/O pins
APPLICATION
Inter-MPU data transfer memory, buffer memory for image processing
system.
BLOCK DIAGRAM
A PORT DATA I/O
NOT READY
OUTPUT
A PORT
ADDRESS INPUT
WRITE
ENABLE INPUT
CHIP
SELECT INPUT
OUTPUT
ENABLE INPUT
Not Ready A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WEA
OEA
CSA
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
13
14
15
16
17
18
19
10
11
12
20
3
2
1
4
5
6
7
8
9
8
8
8 bits
ROW/COLUMN
OEA
I/O BUFFER
CONTROL
DECODER
CIRCUIT
WEA
A
A
0
7
A
A
MEMORY ARRAY OF
256-WORD 8-BIT
CONFIGURATION
ARBITRATION
CIRCUIT
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
NOT READY
OUTPUT
OUTPUT ENABLE
INPUT
PIN CONFIGURATION (Top view)
A PORT
ADDRESS
INPUT
A PORT
DATA I/O
A
A
42
21
0
7
B
B
Not Ready A
V
GND
CC
WEB
ROW/COLUMN
I/O BUFFER
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WEA
GND
CONTROL
OEA
CSA
DECODER
A
A
A
A
A
A
A
A
CIRCUIT
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
M66220SP/FP
Outline 42P4B
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
OEB
MITSUBISHI DIGITAL ASSP
MITSUBISHI DIGITAL ASSP
8
8
42P2R-A
256
32
31
30
M66220SP/FP
39
40
41
38
22
23
24
25
26
27
28
29
37
36
35
34
33
256
Not Ready B
WEB
CSB
OEB
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8-BIT MAIL-BOX
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
V
CSB
WEB
Not Ready B
OEB
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B PORT
ADDRESS INPUT
8-BIT MAIL-BOX
CC
0
1
2
3
4
5
6
7
WRITE
ENABLE INPUT
CHIP
SELECT INPUT
OUTPUT
ENABLE INPUT
B
B
B
B
B
B
B
B
7
6
5
4
3
2
1
0
B PORT DATA I/O
B
B
B
B
B
B
B
B
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
OUTPUT ENABLE
INPUT
B PORT
ADDRESS
INPUT
B PORT
DATA I/O
NOT READY
OUTPUT
NOT READY
OUTPUT
1

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m66220sp Summary of contents

Page 1

... OEB WEB I/O BUFFER MEMORY ARRAY OF 256-WORD 8-BIT ROW/COLUMN CONFIGURATION DECODER 21 GND MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX 256 8-BIT MAIL-BOX CHIP SELECT 41 CSB INPUT WRITE ENABLE 40 WEB INPUT NOT READY 39 Not Ready B OUTPUT OUTPUT ENABLE ...

Page 2

... B port is set to the write mode for memory port is set to the read mode for memory. I/O pin I CC High impedance Stand-by D Operation IN D Operation OUT High impedance Operation MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX is specified. Data at the specified address 7 Operation ...

Page 3

... MITSUBISHI DIGITAL ASSP M66220SP/FP 256 This comes into question. When both ports are operating in the write mode as given in(4), reverse data is written into each port and the contents of memory may become uncertain ...

Page 4

... A port Mode setting Access Not Ready A Read , H , Read L , Write H , Write L , Read H L Read , H Write Write L Arbitration Resolved MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX CSA = CSB = “L” B port Access Not Ready Arbitration Resolved A ...

Page 5

... IN CSA or CSB > V – 0.2V CC Another input V > V – 0. < 0.2V 0mA IN OUT (Active port output pin open and MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX Ratings Unit –0.3 ~ +7.0 V –0 0 700 mW –65 ~ 150 C Unit Limits Unit Typ ...

Page 6

... NO t Write hold time from Not Ready ( 10%, unless otherwise noted) CC Parameter = 5V 10%, unless otherwise noted) CC Parameter = 5V 10%, unless otherwise noted) CC Parameter MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX Limits Unit Min. Typ. Max ...

Page 7

... Read cycle No.1 (Address control) ( v(A) I/O ~I Previous cycle data (D ) OUT Read cycle No.2 (CS control en(CS) OE I/O ~I OUT High impedance ) a(A) Data output determined a(A) t a(CS) t a(OE) t en(OE) Data output determined MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX t v(A) t dis(CS) t dis(OE) 7 ...

Page 8

... Do not apply any negative-phase signal from outside when an I/O pin is in output state. 9: The shaded part means a state in which a signal can be “H” or “L” su(A-WEH) t su(CS rec(WE) w(WE su(D) h(D) Data input determined su(A-WEH su(CS) rec(WE) t w(WE h(D) su(D) Data input determined t dis(WE) MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX ...

Page 9

... When the address input is determined before CS transition to “L” Address matching t t NAA NDA t v(A) t a(A) Address A = Address B Address matching t APS t t NAC NDC t en(CS) t a(CS) Address A = Address B MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX Address not matching t NO Data output determined t NO Data output determined 9 ...

Page 10

... WEB (WEA) I/O B~I (I/O A~I I/O B~I (I/O A~I OUT NAA NDA t su(A-WEH su(A) w(WE) t su(D) Data input determined tdis (WE NAC NDC t su(CS) tw (WE en(CS) dis(WE) Address A = Address B MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX h(D) t en(WE su(D) h(D) Data input determined t en(WE) ...

Page 11

... Figure (The capacitance includes stray wiring capacitance and the probe input capacitance 1250 I/O 775 100pF Fig 1. I/O Output Load = 1250 I/O 775 5pF Fig 2. I/O Output Load (to ten, tdis) MITSUBISHI DIGITAL ASSP M66220SP/FP 256 8-BIT MAIL-BOX + 5V 575 Not Ready 50pF Fig 3. Not Ready Output Load 11 ...

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