adm8513 Infineon Technologies Corporation, adm8513 Datasheet - Page 65

• Manufacturer Part Number: adm8513
• Description: Usb-to-10/100 Mbps Ethernet Lan Controller
• Manufacturer: Infineon Technologies Corporation

Table 72
Register Short Name
ANLPA
ANE
The register is addressed wordwise.
Table 73
Mode
read/write
read
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
Data Sheet
Registers Overview (cont’d)
Register Access Types
Symbol Description HW
rw
r
ro
rv
lhsc
llsc
lhmk
llmk
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Register Long Name
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
65
Description SW
Register is readable and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is readable and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is readable and writable by SW.
Offset Address
5
6
H
H
Registers Description
Rev. 1.21, 2005-12-05
Page Number
72
72
Data Sheet
ADM8513