at89c51cc02ua-tdsum ATMEL Corporation, at89c51cc02ua-tdsum Datasheet - Page 59
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at89c51cc02ua-tdsum
Manufacturer Part Number
at89c51cc02ua-tdsum
Description
At89c51cc02, T89c51cc02 Enhanced 8-bit Microcontroller With Can Controller And Flash
Manufacturer
ATMEL Corporation
Datasheet
1.AT89C51CC02UA-TDSUM.pdf
(159 pages)
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Figure 26. Timer/Counter x (x= 0 or 1) in Mode 2
Mode 3 (Two 8-bit Timers)
Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit Counters
Timer 1
4126L–CAN–01/08
See section “Clock”
See section “Clock”
INT0#
INTx#
CLOCK
CLOCK
CLOCK
T0
FTx
Tx
FTx
FTx
TMOD Reg
GATEx
GATE0
TMOD.3
÷ 6
÷ 6
÷ 6
TMOD Reg
TMOD.2
C/Tx#
C/T0#
Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit
Timers (See Figure 27). This mode is provided for applications requiring an additional 8-
bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-
ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a
Timer function (counting F
run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode
3.
Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-
ing comments help to understand the differences:
•
•
•
0
1
0
1
TCON Reg
TCON.4
TRx
TR0
Timer 1 functions as either a Timer or event Counter in three modes of operation.
Figure 24 to Figure 26 show the logical configuration for modes 0, 1, and 2. Timer
1’s mode 3 is a hold-count mode.
Timer 1 is controlled by the four high-order bits of TMOD register (See Figure 39)
and bits 2, 3, 6 and 7 of TCON register (See Figure 38). TMOD register selects the
method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of
operation (M11 and M01). TCON register provides Timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type
control bit (IT1).
Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best
suited for this purpose.
TCON.6
TR1
PER
/6) and takes over use of the Timer 1 interrupt (TF1) and
(8 bits)
(8 bits)
(8 bits)
(8 bits)
THx
TH0
TLx
TL0
Overflow
Overflow
Overflow
TCON Reg
AT/T89C51CC02
TCON.5
TCON.7
TFx
TF0
TF1
Timer x
Interrupt
Request
Timer 0
Interrupt
Request
Timer 1
Interrupt
Request
59
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