at89lp216-20xi ATMEL Corporation, at89lp216-20xi Datasheet
at89lp216-20xi
Related parts for at89lp216-20xi
at89lp216-20xi Summary of contents
Page 1
... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instruc- tions to execute in 12 clock cycles. In the AT89LP216 CPU, instructions need only clock cycles providing times more throughput than the stan- dard 8051. Seventy percent of instructions need only as many clock cycles as they ® ...
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... RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP216 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter ...
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... Pin Description Table 3-1. AT89LP216 Pin Description Pin Symbol Type Description I/O P1.5: User-configurable I/O Port 1 bit 5. I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin 1 P1 input. I GPI5: General-purpose Interrupt input 5. I/O P1.7: User-configurable I/O Port 1 bit 7. I/O 2 P1.7 SCK: SPI Clock. When configured as master, this pin is an output. When configured as slave, this pin is an input. ...
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... Figure 4-1. 5. Comparison to Standard 8051 The AT89LP216 is part of a family of devices with enhanced features that are fully binary com- patible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051 ...
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... I/O Ports The I/O ports of the AT89LP216 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0 and P3M0 SFRs ...
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... Reset The RST pin of the AT89LP216 is active-low as compared with the active high reset in the stan- dard 8051. In addition, the RST pin is sampled every clock cycle and must be held low for a minimum of two clock cycles, instead of 24 clock cycles recognized as a valid reset. ...
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... Data Memory The AT89LP216 contains 128 bytes of general SRAM data memory plus 128 bytes of I/O mem- ory mapped into a single 8-bit address space. The 128 bytes of data memory may be accessed through both direct and indirect addressing of the lower 128 byte addresses. The 128 bytes of I/O memory reside in the upper 128-byte address space be accessed through direct addressing and contains the Special Function Registers (SFRs) ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 7-1. AT89LP216 SFR Map and Reset Values 8 9 0F8H ...
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... Enhanced CPU The AT89LP216 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... AT89LP216). Violating the physical space limits may cause unknown program behavior. With the CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, and JNZ condi- tional branching instructions, the same previous rule applies ...
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... System Clock Out When the AT89LP216 is configured to use either an external clock or the internal RC oscillator, a divided version of the system clock may be output on XTAL2 (P3.3). The clock out feature is enabled by setting the COE bit in CLKREG. The two CDV bits determine the clock divide ratio. ...
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... During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP216 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. ...
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... RST RST (RST Controlled Externally approximately 92 µs ± 5%. POR (Table 10-1). The start-up delay should be selected to provide enough settling and the selected clock source. The Start-Up Time fuses also control the length of CC AT89LP216 V POR (RST Tied RHD ...
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... SUT Fuse 1 10.2 Brown-out Reset The AT89LP216 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD is nomi- nally 2.2V. The purpose of the BOD is to ensure that if V the system will gracefully enter reset without the possibility of errors induced by incorrect execu- tion ...
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... WDRST register. A software reset will set the SWRST bit in WDT- CON. See “Software Reset” on page 58. 11. Power Saving Modes The AT89LP216 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. 11.1 Idle Mode Setting the IDL bit in PCON enters idle mode ...
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... CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See a two clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will remain in reset until RST is brought high. AT89LP216 16 t SUT Figure 11-3 ...
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... RST or BOD (i.e. warm resets). GF1, GF0 General-purpose Flags PD Power-down bit. Setting this bit activates power-down operation. IDL Idle Mode bit. Setting this bit activates Idle mode operation 3621B–MICRO–11/07 t SUT PWDEX POF GF1 AT89LP216 Reset Value = 000X 0000B GF0 PD IDL ...
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... Interrupts The AT89LP216 provides 7 interrupt sources: two external interrupts, two timer interrupts, a serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register IE ...
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... See 3621B–MICRO–11/07 Interrupt Vector Addresses Source RST or POR or BOD IE0 TF0 IE1 TF1 SPIF GPIF CF Figure 12-1 and Figure 12-2. AT89LP216 Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 19 ...
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... Comparator Interrupt Enable EGP General-purpose Interrupt Enable ES Serial Port Interrupt Enable ET1 Timer 1 Interrupt Enable EX1 External Interrupt 1 Enable ET0 Timer 0 Interrupt Enable EX0 External Interrupt 0 Enable . AT89LP216 IE0 Ack. Cur. Instr. LCALL 1st ISR Instr. 1 Ack. RETI 4 Cyc. Instr. EGP ...
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... External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High 3621B–MICRO–11/07 PGP PS PT1 PGH PSH PT1H AT89LP216 Reset Value = X000 0000B PX1 PT0 PX0 Reset Value = X000 0000B PX1H PT0H PX0H ...
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... I/O Ports The AT89LP216 can be configured for between 9 and 12 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in tolerant, that is they can be pulled up or driven to 5.5V even when operating at a lower V as 3V. Table 13-1. Clock Source External Crystal or Resonator External Clock Internal RC Oscillator 13 ...
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... When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high. The quasi-bidirectional port configuration is shown in cuitry of P1.3, P3.2 and P3.3 is not disabled during Power-down (see Figure 13-1. Quasi-bidirectional Output 3621B–MICRO–11/07 1 Clock Delay (D Flip-Flop) From Port Register AT89LP216 Figure 13-1. The input cir- Figure 13-3 ...
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... The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in P1.3, P3.2 and P3.3 is not disabled during Power-down (see AT89LP216 24 level and must be taken into consideration. CC ...
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... Port 1 Analog Functions The AT89LP216 incorporates an analog comparator. In order to give the best analog perfor- mance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in inputs on P1 ...
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... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP216 share functionality with the various I/Os needed for the peripheral units. fun ction s are co nne cted to the pins gic AN D fashion rder ble th e alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...
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... Enhanced Timer/Counters The AT89LP216 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register increase every clock cycle by default. Thus, the register counts clock cycles. Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator frequency. ...
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... RH1/RL1 and the overflow flag bit in TCON is set. See gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the same for Timer/Counter 0. Figure 14-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload AT89LP216 28 OSC ÷TPS C ...
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... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP216 can appear to have three Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. IE0 Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. IT0 Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. AT89LP216 30 TF0 TR0 IE1 ...
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... Control Mode Timer 0 low-byte Timer 1 low-byte Timer 0 high-byte Timer 1 high-byte Mode Timer 0 reload low-byte Timer 1 reload low-byte Timer 0 reload high-byte Timer 1 reload high-byte AT89LP216 Reset Value = 0000 0000B C Timer0 Timer 0 gate bit Timer 0 counter/timer select bit Timer 0 M1 bit ...
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... PSC00 14.5 Pulse Width Modulation On the AT89LP216, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetri- cal (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/T must be set to “0” when in PWM mode and the T0 (P3.4) and T1 (P3.5) must be configured in an output mode ...
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... Oscillator Frequency ------------------------------------------------------ - Mode out 256 Mode 0: Duty Cycle % ÷TPS OSC Control TR1 GATE Oscillator Frequency Mode 1: ------------------------------------------------------ - f = out 256 Mode 1: Duty Cycle % AT89LP216 1 × ------------------- - + 1 1 PSC0 TPS + × 2 RH0 × ----------- - = 100 256 RH1 (8 Bits) TL1 OCR1 (8 Bits) = ...
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... Timer 1 in PWM Mode 2 is identical to Timer 0. PWM Mode 2 can be used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following formula gives the output frequency for Timer 0 in PWM Mode 2. Figure 14-8. Timer/Counter 1 PWM Mode 2 Note: AT89LP216 34 ÷TPS OSC Control ...
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... TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP216 can appear to have three Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 ...
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... External Interrupts When the AT89LP216 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. The external interrupts can be pro- grammed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered ...
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... P1.x active. Must be cleared by software. 3621B–MICRO–11/07 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 GPIEN3 GPIF5 GPIF4 GPIF3 AT89LP216 Reset Value = 0000 0000B GPLS2 GPLS1 GPLS0 Reset Value = 0000 0000B GPIEN2 GPIEN1 GPIEN0 Reset Value = 0000 0000B GPIF2 GPIF1 GPIF0 2 ...
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... Serial Interface The serial interface on the AT89LP216 implements a Universal Asynchronous Receiver/Trans- mitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 • ...
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... SM2 REN TB8 5 4 SM1 Mode Description 0 0 shift register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART AT89LP216 Reset Value = 0000 0000B RB8 (2) Baud Rate f /2 osc variable (Timer /16 osc osc variable (Timer 1) RI ...
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... Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. AT89LP216 40 Oscillator Frequency Mode 0 Baud Rate ...
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... Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) f (MHz) OSC 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 shows a simplified functional diagram of the serial port in Mode 0 and associ- AT89LP216 Timer 1 SMOD1 C/T Mode ...
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... Figure 17-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) AT89LP216 42 INTERNAL BUS “1“ INTERNAL BUS 3621B–MICRO–11/07 ...
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... Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP216, the baud rate is determined by the Timer 1 overflow rate. plified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “ ...
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... DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP216 44 INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...
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... RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 3621B–MICRO–11/07 show a functional diagram of the serial port in Modes 2 and 3. The and Either SM2 = 0 or the received 9th data bit = 1 AT89LP216 45 ...
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... Figure 17-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP216 46 INTERNAL BUS INTERNAL BUS 3621B–MICRO–11/07 ...
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... RX CLOCK SEND TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP216 TXD SHIFT D6 D7 TB8 STOP BIT RB8 STOP BIT 47 ...
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... A unique address for slave 1 would be 1100 0001 since a “1” in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. AT89LP216 48 SADDR = 1100 0000 ...
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... UART drivers which do not make use of this feature. 18. Serial Peripheral Interface The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the AT89LP216 and peripheral devices or between multiple AT89LP216 devices. The SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...
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... WCOL, and continues transmission without stopping and restarting the clock generator. As long as the CPU can keep the write buffer full in this manner, multiple bytes may be transferred with minimal latency between bytes. AT89LP216 50 MSB Master ...
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... SPD7 SPD6 Bit 7 6 3621B–MICRO–11/07 DORD MSTR CPOL SPD5 SPD4 SPD3 AT89LP216 Reset Value = 0000 0000B CPHA SPR1 SPR0 follows: OSC. Reset Value = 00H (after cold reset) unchanged (after warm reset) SPD2 SPD1 SPD0 ...
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... DISSO bit. Enhanced SPI mode select bit. When ENH = 0, SPI is in normal mode, i.e. without write double buffering. ENH When ENH = 1, SPI is in enhanced mode with write double buffering. The Tx buffer shares the same address with the SPDR register. AT89LP216 52 LDEN – – ...
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... LATCH CLK Oscillator MSB Divider ÷4÷8÷32÷64 SPI Clock (Mater) Select MSTR SPE SPI Control 8 SPI Status Register 8 SPI Interrupt Internal Request Data Bus AT89LP216 7 Serial Slave 2:1 D MUX LATCH CLK Parallel Slave (Read Buffer LATCH CLK LSB ...
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... Figure 18-5. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. AT89LP216 54 18-5. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL MSB ...
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... Analog Comparator A single analog comparator is provided on the AT89LP216. The analog comparator has the fol- lowing features: • Comparator Output Flag and Interrupt • Selectable Interrupt Condition – High- or Low-level – Rising- or Falling-edge – Output Toggle • Hardware Debouncing Modes Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0]) is greater than the negative input AIN1 (P1 ...
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... Note: 1. Debouncing modes require the use of Timer 1 to generate the sampling delay. AT89LP216 56 CIDL CF CEN Interrupt Mode Negative (Low) level Positive edge (1) Toggle with debouncing (1) Positive edge with debouncing Negative edge Toggle (1) ...
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... The WDT time-out period is dependent on the system clock frequency. ------------------------------------------------------ - Time-out Period = Oscillator Frequency MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP216 (1) Period PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K ( ) + ...
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... Software Reset A Software Reset of the AT89LP216 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...
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... The AT89LP216 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP216 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP216 may take clock cycles to complete. The execution times of most instructions may be computed using Table 21-1 ...
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... ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A AT89LP216 60 Instruction Execution Times and Exceptions (Continued) Bytes Bytes ...
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... Instruction Execution Times and Exceptions (Continued) Bytes AT89LP216 Clock Cycles 8051 AT89LP Hex Code 12 1 E8- E6- F8- A8- 78- 88- ...
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... RETI AJMP addr11 LJMP addr16 JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP BREAK Note: AT89LP216 62 Instruction Execution Times and Exceptions (Continued) Bytes Bytes ...
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... On-Chip Debug System The AT89LP216 On-Chip Debug (OCD) System uses a two-wire serial interface to control pro- gram flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • ...
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... XTAL1/P3.2. The INT0, INT1 and CLKOUT functions cannot be emulated in this mode. • The AT89LP216 does not support In-Application Programming and therefore the device must be reset before changing the program code during debugging. This includes the insertion/deletion of software breakpoints. ...
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... SPI master, and the target system always operates as the SPI slave. To enter or remain in In-System Programming mode the device’s reset line (RST) must be held active (low). With the addition of VCC and GND, an AT89LP216 microcontroller can be programmed with a mini- mum of seven connections as shown in Figure 23-1. In-System Programming Device Connections 3621B– ...
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... The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP216 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In- System programmer ...
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... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP216 allocates 5 bits for byte address and 6 bits for page address. The page to be accessed is always fixed by the page address as transmitted ...
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... Figure 23-3. Command Sequence Flow Chart Figure 23-4. ISP Command Packet SS SCK MOSI Preamble 1 MISO X AT89LP216 68 Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Address +1 Data Preamble 2 ...
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... Fuse definitions. for Lock Bit definitions. 00H = 1EH 01H = 29H 02H = FFH AT89LP216 Addr Low Data 0 – – – – – xxxx xxxx Status Out xxxb bbbb DataIn 0 ... DataIn n aaab bbbb DataIn 0 ...
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... Flash Security The AT89LP216 provides two Lock Bits for Flash Code Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in Lock bits can only be erased (set to FFh) by Chip Erase. Lock bit mode 2 disables programming of all memory spaces, including the User Signature Array and User Configuration Fuses ...
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... User Configuration Fuses The AT89LP216 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in ming 00h to their locations. Programming FFh to fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...
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... Drive SCK low. 2. Wait at least t 3. Tristate MOSI. 4. Wait at least t 5. Wait no more than t Figure 23-6. Serial Programming Power-down Sequence V RST SCK MISO MOSI AT89LP216 72 75. 14). . and drive SS high. PWRUP for the internal Power-on Reset to complete. The value of t SUT PWRUP ...
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... SS high. SSD and bring RST high. SSZ and tristate SS. RHZ V CC XTAL1 RST t SS SSZ t SSD SCK MISO MOSI The waveforms on this page are not to scale. AT89LP216 t RLZ t t STL ZSS t SSE HIGH Z HIGH Z t RHZ HIGH Z HIGH Z 73 ...
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... CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 23-9. ISP Byte Sequence Figure 23-10. Serial Programming Interface Timing SCK MISO MOSI AT89LP216 74 Figure 23-9. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, SCK MOSI 7 ...
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... SS Disable Lag Time SSD SCK Setup to SS Low ZSS SCK Hold after SS High SSZ Write Cycle Time WR Write Cycle with Auto-Erase Time Chip Erase Cycle Time ERS independent SCK CLCL AT89LP216 23-6, Figure 23-7, Figure 23-8, and Min Max 100 CLCL ...
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... Under steady state (non-transient) conditions, I Maximum I per port pin Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89LP216 76 *NOTICE: Condition mA 2.7V 85° ± 10 -80 µA, V ...
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... Serial Output Hold Time SOH t Serial Output Valid Time SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD 3621B–MICRO–11/07 AT89LP216 Min Max 41.6 4t CLCL SCK SCK ...
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... SCK (CPOL = 1) MISO MOSI Figure 24-2. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-3. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP216 SCK t t SHSL SLSH t t SLSH SHSL t t SOH SOV t t ...
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... External Clock Drive External Clock Drive Waveform Figure 24-5. Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL 3621B–MICRO–11/ 2.4V to 5.5V CC Min Max AT89LP216 Units MHz ...
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... V IH (1) 24.6.2 Float Waveform Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V AT89LP216 80 = 2.4V to 5.5V and Load Capacitance = 80 pF ...
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... CLOCK SIGNAL XTAL1 RST CC (NC) XTAL2 CLOCK SIGNAL XTAL1 V SS Tests in Active and Idle Modes CHCL CHCX V RST CC (NC) XTAL2 XTAL1 VSS AT89LP216 CLCH CHCL t CHCX t CLCH t CLCL = ...
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... Ordering Information 25.1 Standard Package Speed Power (MHz) Supply Ordering Code AT89LP216-20PI 20 2.4V to 5.5V AT89LP216-20SI AT89LP216-20XI 25.2 Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89LP216-20PU 20 2.4V to 5.5V AT89LP216-20SU AT89LP216-20XU 16P3 16-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 16S2 16-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) 16X 16-lead, 0.173” ...
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... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3621B–MICRO–11/07 D PIN TITLE 16P3, 16-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) AT89LP216 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – 5.334 A1 0.381 – – D 19.81 – 20.32 ...
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... The lead width "B", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP216 ...
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... Orchard Parkway San Jose, CA 95131 R 3621B–MICRO–11/ TITLE 16X, 16-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) AT89LP216 End View L L Ø Ø COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – ...
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... Revision History Revision No. Revision A – July 2006 Revision B – Nov. 2007 AT89LP216 86 History • Initial Release • Removed “Preliminary” status from the datasheet. 3621B–MICRO–11/07 ...
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... Memory Organization .............................................................................. 6 7. Special Function Registers ..................................................................... 8 8. Enhanced CPU ......................................................................................... 9 9. System Clock ......................................................................................... 11 10. Reset ....................................................................................................... 12 11. Power Saving Modes ............................................................................. 15 3621B–MICRO–11/07 2.1 AT89LP216: 16-lead PDIP/SOIC/TSSOP ..............................................................2 5.1 System Clock ..........................................................................................................4 5.2 Instruction Execution with Single-cycle Fetch .........................................................4 5.3 Interrupt Handling ...................................................................................................5 5.4 Timer/Counters .......................................................................................................5 5.5 Serial Port ...............................................................................................................5 5.6 Watchdog Timer .....................................................................................................5 5.7 I/O Ports ..................................................................................................................5 5.8 Reset ......................................................................................................................6 6.1 Program Memory ....................................................................................................6 6 ...
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... General-purpose Interrupts .................................................................. 36 17. Serial Interface ....................................................................................... 38 18. Serial Peripheral Interface ..................................................................... 49 19. Analog Comparator ............................................................................... 55 20. Programmable Watchdog Timer ........................................................... 57 21. Instruction Set Summary ...................................................................... 59 22. On-Chip Debug System ......................................................................... 63 AT89LP216 ii 12.1 Interrupt Response Time ......................................................................................19 13.1 Port Configuration ................................................................................................. 22 13.2 Port 1 Analog Functions ....................................................................................... 25 13.3 Port Read-Modify-Write ........................................................................................ 25 13.4 Port Alternate Functions ....................................................................................... 26 14.1 Mode 0 – Variable Width Timer/Counter .............................................................. 27 14.2 Mode 1 – ...
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... User Configuration Fuses ..................................................................................... 71 23.8 Programming Interface Timing ............................................................................. 72 24.1 Absolute Maximum Ratings* ................................................................................. 76 24.2 DC Characteristics ................................................................................................ 76 24.3 Serial Peripheral Interface Timing ....................................................................... 77 24.4 External Clock Drive ............................................................................................. 79 24.5 Serial Port Timing: Shift Register Mode ................................................................ 80 24.6 Test Conditions ..................................................................................................... 80 25.1 Standard Package ................................................................................................ 82 25.2 Green Package Option (Pb/Halide-free) ............................................................... 82 26.1 16P3 – PDIP .........................................................................................................83 26.2 16S2 – SOIC .........................................................................................................84 26.3 16X – TSSOP .......................................................................................................85 AT89LP216 iii ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...