saf-xc888cm-8ffi5v Infineon Technologies Corporation, saf-xc888cm-8ffi5v Datasheet - Page 44

• Manufacturer Part Number: saf-xc888cm-8ffi5v
• Description: 8-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

Table 9
Addr Register Name
BE H
BF H
3.2.4.6
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 10
Addr Register Name
RMAP = 0
B2 H
RMAP = 0, PAGE 0
80 H
86 H
90 H
91 H
92 H
93 H
A0 H
A1 H
B0 H
B1 H
C8 H
C9 H
Data Sheet
WDTL
Watchdog Timer Register Low
WDTH
Watchdog Timer Register High
PORT_PAGE
Page Register
P0_DATA
P0 Data Register
P0_DIR
P0 Direction Register
P1_DATA
P1 Data Register
P1_DIR
P1 Direction Register
P5_DATA
P5 Data Register
P5_DIR
P5 Direction Register
P2_DATA
P2 Data Register
P2_DIR
P2 Direction Register
P3_DATA
P3 Data Register
P3_DIR
P3 Direction Register
P4_DATA
P4 Data Register
P4_DIR
P4 Direction Register
Port Registers
WDT Register Overview (cont’d)
Port Register Overview
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Reset: 00 H
Bit
Bit Field
Type
Bit Field
Type
Bit
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
Bit Field
Type
P7
P7
P7
P7
P7
P7
P7
P7
P7
P7
P7
P7
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
7
7
OP
w
37
P6
P6
P6
P6
P6
P6
P6
P6
P6
P6
P6
P6
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
6
6
P5
P5
P5
P5
P5
P5
P5
P5
P5
P5
P5
P5
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
5
5
STNR
w
P4
P4
P4
P4
P4
P4
P4
P4
P4
P4
P4
P4
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
4
4
WDT
WDT
rh
rh
Functional Description
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
3
0
r
XC886/888CLM
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
2
2
V1.1, 2009-01
PAGE
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
1
1
P0
P0
P0
P0
P0
P0
P0
P0
P0
P0
P0
P0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0