saf-xc866-4rri3v Infineon Technologies Corporation, saf-xc866-4rri3v Datasheet - Page 53

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saf-xc866-4rri3v

Manufacturer Part Number
saf-xc866-4rri3v
Description
8-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
3.4.3
Each interrupt source, except for NMI, can be individually programmed to one of the four
possible priority levels. The NMI has the highest priority and supersedes all other
interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are
available to program the priority level of each non-NMI interrupt vector.
A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another
interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot
be interrupted by any other interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority are
received simultaneously, then an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence shown in
Table 18
Source
Non-Maskable Interrupt (NMI)
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
UART Interrupt
Timer 2,Fractional Divider, LIN Interrupts 6
ADC Interrupt
SSC Interrupt
External Interrupt 2
External Interrupt [6:3]
CCU6 Interrupt Node Pointer 0
CCU6 Interrupt Node Pointer 1
CCU6 Interrupt Node Pointer 2
CCU6 Interrupt Node Pointer 3
Data Sheet
Interrupt Priority
Priority Structure within Interrupt Level
49
Level
(highest)
1
2
3
4
5
7
8
9
10
11
12
13
14
Table
18.
Functional Description
V1.2, 2007-10
XC866

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