ds64ev100sdx National Semiconductor Corporation, ds64ev100sdx Datasheet - Page 2

• Manufacturer Part Number: ds64ev100sdx
• Description: Programmable Single Equalizer
• Manufacturer: National Semiconductor Corporation

www.national.com
HIGH SPEED DIFFERENTIAL I/O
IN+
IN−
OUT+
OUT−
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
POWER
V
GND
Exposed
Pad
OTHER
NC
Pin Name
DD
Pin Diagram
Pin Descriptions
Note: I = Input, O = Output
Pin Number
2, 6, 9, 10,
PAD
12
11
14
13
3
4
7
8
5
1
I, CMOS BST_2, BST_1, and BST_0 select the equalizer strength for EQ channel 1. BST_2 is internally
I, Power V
I, Power Ground reference. GND should be tied to a solid ground plane through a low impedance path.
I, Power Ground reference. The exposed pad at the center of the package must be connected to ground
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
I, CML
Type
I/O,
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating
resistor is connected between IN+ and IN-.
terminating resistor connects OUT+ to V
pulled high. BST_1 and BST_0 are internally pulled low.
path. A 0.01μF bypass capacitor should be connected between each V
plane of the board.
Reserved. Do not connect.
DD
= 2.5V ±5% or 3.3V ±10%. V
See NS Package Number SDA14A
3mm x 4mm 14-Pin LLP Package
Order number DS64EV100
Top View
2
DD
pins should be tied to V
DD
Description
and OUT- to V
20196402
DD
DD
.
plane through low inductance
DD
pin to GND planes.