vsc7216-01 ETC-unknow, vsc7216-01 Datasheet
vsc7216-01
Related parts for vsc7216-01
vsc7216-01 Summary of contents
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... Encoder/Decoder Bypass Operation TM • “ASIC-Friendly ” Timing Options for Transmitter Parallel Input Data • Elastic Buffers for Intra/Inter-Chip Cable Deskewing and Channel-to-Channel Alignment • Tx/Rx Rate Matching via IDLE Insertion/Deletion • Compatible with VSC7211/7212/7214 VSC7216-01 Block Diagram TRANSMITTER PTXEND 8 8 TD(7:0) 8B/10B C/ ...
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... TTL (using REFCLKP and leaving REFCLKN open). Clock Synthesizer Depending on the state of the DUAL input, the VSC7216-01 clock synthesizer multiplies the reference frequency provided on the REFCLK input by 10 (DUAL is LOW (DUAL is HIGH) to achieve a baud rate clock between 0.98GHz and 1.36GHz. The on-chip PLL uses a single external 0.1µF capacitor, connected between CAP0 and CAP1, to control the Loop Filter ...
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... Transmitter Functional Description Transmitter Data Bus Each VSC7216-01 transmit channel has an 8-bit input transmit data character, Tn(7:0), and two control inputs, C/Dn and WSENn. The C/Dn input determines whether a normal data character or a special “K- character” is transmitted, and the WSENn input initiates transmission of a 16-character “Word Sync Sequence” ...
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... WSENn Page 4 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION Valid Valid Valid Valid Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Valid Valid G52352-0, Rev 3.2 05/05/01 ...
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... Preliminary Datasheet VSC7216-01 Figure 4: Transmit Timing, TMODE(2:0) = 11X (“ASIC-Friendly” Timing) TBCA or TBCn Tn(7:0) C/Dn WSENn 8B/10B Encoder Each channel contains an 8B/10B encoder which translates the 8-bit input data on Tn(7:0) into a 10-bit encoded data character. C/Dn inputs are also provided in each channel which, along with KCHAR, allow the transmission of special Fibre Channel Kxx ...
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... Fibre Channel ( VSC7125) and Gigabit Ethernet markets (VSC7135). Word Sync Generation The VSC7216-01 can perform channel alignment (also referred to as “word alignment” or “word sync”), meaning that the four receive data output streams are aligned such that the same 4-byte word presented to the four transmit channel inputs for serialization will be transferred on the receive channel parallel outputs ...
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... Preliminary Datasheet VSC7216-01 Serializer The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a multiplexer which serializes the parallel data using the synthesized transmit clock. The least significant bit of the 10B data is transmitted first. Each channel has both primary and redundant serial output ports, PTXn and RTXn respectively, which consist of differential PECL output buffers operating at either times the REFCLK rate ...
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... Re-synchronization is always enabled and cannot be turned off when ENDEC is HIGH. After character re-synchronization the VSC7216-01 ensures that within a link, the 8-bit data sent to the transmitting VSC7216-01 will be recovered by the receiving VSC7216-01 in the same bit locations as the transmitter (i.e., Tn(7:0) = Rn(7:0)). When ENDEC is LOW, “ ...
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... Word Sync Event to recenter all elasticity buffers. Otherwise, data corruption could occur. The VSC7216-01 presents recovered data on Rn(7:0) and status on IDLEn, KCHn and ERRn. These outputs are timed either to each channel’s own recovered clock (RCLKn/RCLKNn), to Channel A’s recovered clock (RCLKA/RCLKNA REFCLK ...
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... If DUAL is LOW, the data is clocked out of the VSC7216-01 only on the rising edge of the selected word clock at 1/10th the baud rate. Timing waveforms for the output data and status are shown in Figure 6, Figure 7 and Figure 8. ...
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... The VSC7216-01 performs channel-to-channel word alignment. In this mode of operation, if the data from all four channels on the transmitting VSC7216-01 (e.g., the 4 Tn(7:0) busses) is viewed as a 32-bit word, then the receiving VSC7216-01 will recover an identical word. For example transmit pattern was ‘ABCD’, © ...
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... Multiple VSC7216-01 devices can also be used in synchronous operation if the skew between all serial input pairs is maintained less than ±6 serial clock bit times. This allows easy implementation of robust systems, and is discussed in greater detail in the Using Multiple VSC7216-01s in Parallel section ...
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... IDLEs will have to be added to or dropped from all the channels at the same time. In order to implement this, one VSC7216-01 is arbitrarily chosen as the “Master” and its WSO output is driven to the WSI inputs of all the receiving VSC7216-01s, including itself. WSO is asserted prior to the VSC7216-01 adding/dropping IDLEs so all the VSC7216-01s will operate simultaneously. WSO uses a simple 3-bit serial protocol, synchronous to the Master channel’ ...
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... Figure 9. The RESYNC state is entered when a 10-bit word has been received which contains the 7-bit Comma pattern (e.g., a K28.5 IDLE character). After entering the RESYNC state, the VSC7216-01 will stay in it until a valid, non-Comma transmission is received, then it transitions to the SYNC_ACQUIRED state indicating a normal operating condition. The RESYNC state is re-entered if four consecutive “ ...
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... Preliminary Datasheet VSC7216-01 Figure 9: State Diagram of the Loss of Synchronization State Machine Valid Comma LOSS_OF_SYNC ERRn=1 KCHn=1 IDLEn=0 Figure 10: State Diagram of the Invalid Transmission Counter Valid 0 Mis-Aligned Comma © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52352-0, Rev 3.2 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com ...
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... Loss of Synchronization: The receiver state machine is in the Loss-of-Sync 2 state. Data on Rn(7:0) is invalid. RESYNC: The receiver state machine is in the Re-Synchronization state. 2 Data on Rn(7: decoded version of K28.1, K28.5 or K28.7. Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Link Status G52352-0, Rev 3.2 05/05/01 ...
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... This allows parallel data on Tn(7: encoded, serialized, looped back, deserialized and decoded. This mode is intended for the system to verify functionality of the local VSC7216-01 prior to attempting to establish an external link. The PTXn and RTXn outputs are unaffected by the state of LBENn(1:0) ...
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... SEMICONDUCTOR CORPORATION Figure 12: BIST Mode Operation LBENn(1:0) RXP/Rn LBTXn Clk/Data PTXn+ PRXn+ Recovery PTXn- PRXn- RTXn+ RRXn+ RTXn- RRXn- PSDETn RSDETn RECEIVER Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 8 Rn(7:0) 8 8B/10B Elastic 10 IDLEn 3 KCHn Buffer Decode ERRn BIST Chk WORDCLK 1 TBERRn } ...
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... In general, the VSC7216-01 low-speed parallel interfaces can be configured so that there are input and output signals that are compatible with their VSC7211 and VSC7214 counterparts. On the transmit interface, the signals Tn(7:0) and C/Dn behave identically on the VSC7216-01 as long as the input timing is referenced to REFCLK (e.g., TMODE(2:0)=000). On the receive interface, the signals Rn(7:0), ERRn, KCHn and IDLEn behave identically on the VSC7216-01 as long as the four receive channels present output data centered around REFCLK (RMODE(1:0)=00) or timed to RCLKA/RCLKNA (RMODE(1:0)=10) ...
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... Receiver Rn(7:0), ERRn, KCHn and IDLEn outputs are synchronous to REFCLK, IDLE insertion/deletion is disabled, and the receive channels are word-aligned. The VSC7216-01 should be configured with RMODE(1:0)=00, FLOCK=1, and WSI connected to its own WSO or to the WSO of another VSC7216-01 if multiple devices are to be used in parallel. The WSI connection allows word alignment to occur, and the FLOCK connection inhibits IDLE insertion/deletion ...
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... Preliminary Datasheet VSC7216-01 AC Specifications Figure 13: Transmit Input Timing Waveforms with TMODE = 000 REFCLK (DUAL=0) REFCLK (DUAL=1) Internal Clock (from PLL) Tn(7:0) C/Dn WSENn Figure 14: Transmit Input Timing Waveforms with TMODE = 10X TBCn (or TBCA) Internal Clock (from PLL) Tn(7:0) C/Dn WSENn Table 10: Transmit Input AC Characteristics with TMODE = 000 or TMODE = 10X ...
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... Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 T S Valid Units Conditions Measured between the valid data bc level of the input and the 1.4V point of TBCn or TBCA bit clock. TX0 ...
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... Preliminary Datasheet VSC7216-01 Figure 17: Receive Output Timing Waveforms with RMODE = REFCLK (DUAL = 0) REFCLK (DUAL = 1) Rn(7:0) TBERRn KCHn IDLEn ERRn PSDETn RSDETn Table 13: Receive Output AC Characteristics with RMODE = Parameters Description REFCLK Rising Edge to TTL T CQ Output Transition REFCLK Rising Edge to TTL ...
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... Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Units Conditions T is the bit period of the incoming data on Rx. Deviation of RCLKn rising ps edge to RCLKNn rising edge. Nominal delay is 10 bit times. ...
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... Internet: www.vitesse.com Multi-Gigabit Interconnect Chip V IH(MIN) V IL(MAX) Conditions DUAL = 0, RATE = 1 DUAL = 1, RATE = 1 DUAL = 0, RATE = 0 DUAL = 1, RATE = 0 | REFCLK (Tx) - REFCLK (Rx max offset between Tx and Rx device REFCLKs on one serial link. Measured at 1.4V Between V and V IL(MAX) IH(MIN) Peak-to-peak jitter at VSC7216-01 REFCLK input. Page 25 ...
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... Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION TTL Input and Output Rise and Fall Time 80% 20 Bit Time Amplitude Eye Width% 25% Parametric Test Load Circuit 50 GND Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 V IH(MIN) V IL(MAX TTL AC Output Load 10pF G52352-0, Rev 3.2 05/05/01 ...
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... Preliminary Datasheet VSC7216-01 DC Characteristics Table 17: DC Characteristics Parameters Description TTL Outputs (Rn(7:0), KCHn, IDLEn, ERRn, RCLKn/RCLKNn, TBERRn, PSDETn, RSDETn, WSO) V TTL output HIGH voltage OH V TTL output LOW voltage OL I TTL output leakage current OZ TTL Inputs (TBCn, Tn(7:0), C/Dn, WSENn, KCHAR, RATE, BIST, LBENn(1:0), TMODE(2:0), RMODE(1:0), DUAL, ...
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... Page 28 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION (1) ) ..................................................................................................0.5V to +3.8V DDX ) ..............................................................................................-55 C Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 +0. 0. +125 +150 ...
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PRXC+ PRXC- RRXC+ RRXC- TD4 C/DD VSSD REFCLKP RRXD+ RRXD- RXP/RC TMODE2 TD0 TD2 TD5 WSEND VDDD RXP/RD VSSD VSSD VDDD TD1 VSSD TD6 PRXD+ PRXD- LBENC1 VDDD TMODE0 TMODE1 TD3 TD7 RTXD+ ...
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... Transmit Buffer ERRor for channel n. When HIGH indicates that the elastic limit of the transmit input skew buffer was exceeded, output timing is same TTL as Rn(7:0). A LOW indicates correct reception of the 256-byte incrementing pattern in BIST mode. Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Pin Description G52352-0, Rev 3.2 05/05/01 ...
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... Preliminary Datasheet VSC7216-01 Pin Name I/O 1R, 2R PTXA+/- 1M, 2M PTXB+/- O 1J, 2J PTXC+/- 1F, 2F PTXD+/- 1T, 2T RTXA+/- 1N, 2N RTXB+/- O 1H, 2H RTXC+/- 1E, 2E RTXD+/- 4N PTXENA 4M PTXENB I 4J PTXENC 4H PTXEND 3P RTXENA 3N RTXENB I 3H RTXENC 3G RTXEND 18P, 19R 20U, 20V RA(7:0) O 17R, 19U 20W, 18T 15V, 15U ...
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... REFCLKN open. If PECL, connect both REFCLKP and REFCLKN. Loop Filter CAPacitor for clock generation PLL. Nominally 0.1µF, Analog amplitude is less than 3V. See the Loop Filter Applications section for more details. Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Pin Description /2 through through a DD G52352-0, Rev 3 ...
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... TTL JTAG Test Access Port test logic reset input N/A Reserved Inputs for future use. Set HIGH for compatibility reasons. RATE Mode. When HIGH, VSC7216-01 runs at full data rate (default TTL mode). When asserted LOW, half-speed data rate is selected. VDD Analog power supply to PLL. ...
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... PECL Output power supply for PTXC. PECL Output power supply for RTXC. PECL Output power supply for PTXD. PECL Output power supply for RTXD. If use of an output is not necessary, leave the power supply pin open. Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 Pin Description G52352-0, Rev 3.2 05/05/01 ...
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... Preliminary Datasheet VSC7216-01 Package Information 1.27 Typ 27.0 BOTTOM VIEW © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 G52352-0, Rev 3.2 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com 05/05/01 VITESSE SEMICONDUCTOR CORPORATION 256-pin BGA ...
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... Multi-Gigabit Interconnect Chip Multi-Gigabit Interconnect Chip Package Thermal Considerations The VSC7216-01 is packaged in a 256-pin, 27mm, thermally-enhanced BGA in a 20x20 array which offers excellent electrical characteristics, good thermal performance and small size. This package uses an industry- standard footprint. The package construction is shown in Figure 23. ...
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... Preliminary Datasheet VSC7216-01 Ordering Information The part number for this product is formed by a combination of the device type and the package style: Device Type Multi-Gigabit Interconnect Chip Marking Information The package is marked with three lines of text as in Figure 24: Pin 1 Identifier Part Number ...
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... Multi-Gigabit Interconnect Chip Page 38 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com VITESSE SEMICONDUCTOR CORPORATION This page left intentionally blank. Internet: www.vitesse.com Preliminary Data Sheet VSC7216-01 VSC7216 G52352-0, Rev 3.2 05/05/01 ...