ata6285n ATMEL Corporation, ata6285n Datasheet
ata6285n
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ata6285n Summary of contents
Page 1
... LiMnO2 battery coin cell, a single-ended antenna for the data transmission and an LF ferrite coil for the wake-up channel. ATA6285N and ATA6286N support TPMS-specific low-current modes even with an active brown-out detection and an interval timer ...
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... Overview 2.1 Application Figure 2-1. Tire Pressure Monitoring System (TPMS) Battery Crystal Frequency 13.56 MHz for 433 MHz application Crystal Frequency 13.125 MHz for 315 MHz application ATA6285N/ATA6286N [Preliminary] 2 VDD XZ Pressure Motion sensor sensor ATA6285N 20 5 ATA6286N ...
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... PC0 multiplexer Temperature sensor IO Ports 2.3 Inter-die Bonding The ATA6285N/ATA6286N are Smart RF Micro Transmitter ICs in MCP (Multi Chip Package) technology. Table 2-1. AVR – Pin PD3 (INT1) – External interrupt input 1 PD4 (ECIN1) – External clock input 1 PD5 (T2O1) – Timer2 modulator output 1 PD6 (T2O2) – ...
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... PB6 7 PB7 8 XT02 9 PB2 10 XT01 11 VS_RF 12 GND 13 NRESET 14 GND GND Note: 1. Internal inter-die connection of the MCP ATA6285N/ATA6286N [Preliminary GND 18 7 LF1 19 6 ATA6285N LF2 20 5 ATA6286N VCC 21 4 PC2 22 3 PC1 23 2 PC0 ...
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... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmegaT. 4958BS–AUTO–01/09 ATA6285N/ATA6286N [Preliminary] Alternate Alternate Function 1 Function 2 – ...
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... Shorter pulses then defined minimum pulse length are not guaranteed to generate a reset. 2.5.7 LF (2..1) Input coil pins for the LF-Receiver. 2.5.8 S (2..0) Measuring input pins for external capacitance sensor elements. 2.5.9 ANT(2, 1) RF-Antenna pins. 2.5.10 XTO(0, 1) External crystal for the internal RF transmitter IC. ATA6285N/ATA6286N [Preliminary] 6 4958BS–AUTO–01/09 ...
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... The embedded core is an extremely low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AVR core achieves throughputs approaching 1 MIPS per MHz allowing the designer to optimize power consumption versus processing speed. 4958BS–AUTO–01/09 ATA6285N/ATA6286N [Preliminary] 8 General Purpose Working Registers 7 ...
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... Block Diagram Figure 3-1. ATA6285N/ATA6286N [Preliminary] 8 Microcontroller Block Diagram Oscillator Watchdog circuit timer 0 Clock Watchdog management oscillator and monitoring EEPROM SRAM debugWIRE Program logic 16 bit bit T1 Temperature 16 bit T/ C3 sensor SPI LF receiver PORT C (x) PORT B (x) Power VCC Supervision POR/ BOD/ ...
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... The AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evalu- ation Kits. 4958BS–AUTO–01/09 ATA6285N/ATA6286N [Preliminary] ® ’s high density non-volatile memory technology. The 9 ...
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... PLL Transmitter IC with Single-ended Output • High output Power (6 dBm) at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Typical Values • Divide by 24 (ATA6285N) and 32 (ATA6286N) Blocks for 13 MHz Crystal Frequencies and for Low XTO Start-up Times • Modulation Scheme ASK/FSK with Internal FSK Switch • ...
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... CLK output activation. This means an additional wait time of necessary before the PA can be switched on and the data transmission can start. This results in a significantly lower time of about 0.85 ms between enabling the ATA6285N/ATA6286N and the beginning of the data transmission which saves battery power especially in tire pressure moni- toring systems ...
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... Transmission with ENABLE = Open 4.5.1.1 ASK Mode The ATA6285N/ATA6286N is activated by ENABLE = open, FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is acti- vated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK ...
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... Transmission with ENABLE = High 4.5.2.1 FSK Mode The ATA6285N/ATA6286N is activated by ENABLE = High, FSK = High and ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is acti- vated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of 250 µ ...
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... Figure 4-4. 4.5.2.2 ASK Mode The ATA6285N/ATA6286N is activated by ENABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK ...
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... CLK Output An output CLK signal of 1.64 MHz (ATA6285N operating at 315 MHz) and 1.69 MHz (ATA6286N operating at 433.92 MHz) is provided for a connected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. ...
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... The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the ATA6285N/ATA6286N external clocking and to wait automatically until the CLK output of the ATA6285N/ATA6286N is activated. After a time period of 250 µs the message can be sent with crystal accuracy. 4.5.6 Output Matching and Power Setting The output power is set by the load impedance of the antenna ...
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... ATA6285N-PNQW ATA6286N-PNQW 6. Package Information Package: QFN_ 5 x 5_32L Exposed pad 3.6 x 3.6 Dimensions in mm Not indicated tolerances ±0.05 Pin1 identification Drawing-No.: 6.543-5124.01-4 Issue: 1; 28.11.05 4958BS–AUTO–01/09 ATA6285N/ATA6286N [Preliminary] Package Frequency QFN32 315 MHz QFN32 433 MHz QFN32 315 MHz QFN32 433 MHz Top ...
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... Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4958BS-AUTO-01/09 ATA6285N/ATA6286N [Preliminary] 18 History ATA6285/ATA6286 renamed in ATA6285N/ATA6286N 4958BS–AUTO–01/09 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...