ad8177 Analog Devices, Inc., ad8177 Datasheet
ad8177
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ad8177 Summary of contents
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... Inputs can be paralleled as well. The AD8177 offers both serial and parallel programming modes. The AD8177 is packaged in a fully populated 26 × 26 ball PBGA package and is available over the extended industrial temperature range of −40°C to +85°C. ...
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... AD8177 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics (Serial Mode) ....................................... 5 Timing Characteristics (Parallel Mode) .................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Power Dissipation......................................................................... 7 ESD Caution.................................................................................. 7 REVISION HISTORY 7/07—Revision 0: Initial Version Pin Configuration and Function Descriptions..............................8 Truth Table and Logic Diagram ............................................... 17 Equivalent Circuits ...
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... IN, CM ΔV /ΔV , ΔV = ±0.5 V CMENC off OUT, CM IN, CM IN, CM ΔV /ΔV , ΔV = ±0.5 V, CMENC on OUT, CM IN, CM IN, CM Any switch configuration Differential Rev Page AD8177 Min Typ Max 500 450 25 1.3 4 1800 1500 300 400 −88 −82 −58 −46 −94 ...
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... AD8177 Parameter SWITCHING CHARACTERISTICS Enable On Time Switching Time Step POWER SUPPLIES Supply Current Supply Voltage Range PSR OPERATING TEMPERATURE RANGE Temperature Range θ JA Conditions 50% UPDATE to 50% output 50% UPDATE to 50% output VPOS, outputs enabled, no load Outputs disabled VNEG, outputs enabled, no load ...
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... TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL SEROUT SER/PAR, CLK, SERIN, UPDATE –20 μA max –1 mA min max I IL −120 μA max μA max AD8177 Unit μ SEROUT 1 mA min ...
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... AD8177 TIMING CHARACTERISTICS (PARALLEL MODE) Table 7. Parameter Parallel Data Setup Time WE Pulse Width Parallel Hold Time WE Pulse Separation WE to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On RST Time LATCHED UPDATE 0 = TRANSPARENT Table 8. Logic Levels ...
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... JA PBGA 15 POWER DISSIPATION Rating The AD8177 is operated with ±2 supplies and can 6 V drive loads down to 100 Ω, resulting in a large range of possible 6 V power dissipations. For this reason, extra care must be taken +0 −2.5 V derating the operating conditions based on ambient temperature. ...
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... AD8177 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VNEG VNEG VNEG NC NC VNEG OPR4 B VNEG VNEG VNEG NC NC VNEG ONR4 C VNEG VNEG VNEG NC NC VNEG OPG4 D VNEG VNEG VNEG NC NC VPOS H4 E VNEG VNEG VNEG VPOS VPOS VPOS VPOS ...
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... VPOS NC NC VNEG VNEG IPB0 VNEG ONR0 OPB0 VPOS NC NC VNEG VNEG INB0 VNEG OPR0 ONB0 VPOS NC NC VNEG VNEG AD8177 VNEG B VNEG C VNEG D VNEG E VNEG F VPOS G OPB3 ONB3 H OPR3 J VNEG VPOS N OPB2 ...
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... AD8177 Table 14. Ball Grid Function Descriptions Ball No. Mnemonic Description A1 VNEG Negative Analog Power Supply. A2 VNEG Negative Analog Power Supply. A3 VNEG Negative Analog Power Supply. A4 INB12 Input Number 12, Negative Phase. A5 IPR12 Input Number 12, Positive Phase. A6 VPOS Positive Analog Power Supply. A7 INB11 Input Number 11, Negative Phase. ...
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... H21 VPOS H22 VPOS H23 H3 H24 OPG3 Rev Page AD8177 Description Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. ...
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... AD8177 Ball No. Mnemonic Description H25 ONR3 Output Number 3, Negative Phase. H26 OPR3 Output Number 3, Positive Phase. J1 INB14 Input Number 14, Negative Phase. J2 IPB14 Input Number 14, Positive Phase. J3 ING14 Input Number 14, Negative Phase. J4 VPOS Positive Analog Power Supply. J5 VPOS Positive Analog Power Supply. ...
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... VNEG T21 VPOS T22 VPOS T23 NC T24 NC Rev Page AD8177 Description Output Number 2, Negative Phase. Output Number 2, Positive Phase. Input Number 7, Positive Phase. Input Number 7, Negative Phase. Input Number 7, Positive Phase. Positive Analog Power Supply. Output Reference with CM Encoding Off. ...
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... AD8177 Ball No. Mnemonic Description T25 NC No Connect. T26 NC No Connect. U1 VNEG Negative Analog Power Supply. U2 VNEG Negative Analog Power Supply. U3 VNEG Negative Analog Power Supply. U4 VPOS Positive Analog Power Supply. U5 VPOS Positive Analog Power Supply. U6 VPOS Positive Analog Power Supply. U7 VPOS Positive Analog Power Supply ...
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... AD21 VPOS AD22 NC AD23 NC AD24 VNEG Rev Page AD8177 Description Negative Analog Power Supply. Negative Analog Power Supply. Input Number 5, Negative Phase. Input Number 5, Positive Phase. Input Number 5, Negative Phase. Positive Analog Power Supply. Positive Analog Power Supply. Positive Analog Power Supply. ...
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... AD8177 Ball No. Mnemonic Description AD25 VNEG Negative Analog Power Supply. AD26 VNEG Negative Analog Power Supply. AE1 VNEG Negative Analog Power Supply. AE2 VNEG Negative Analog Power Supply. AE3 VNEG Negative Analog Power Supply. AE4 INR4 Input Number 4, Negative Phase. AE5 IPB4 Input Number 4, Positive Phase ...
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... D0 through D4 is loaded into the shift register location addressed by A0 through A2. Data is not applied to the switch array Switch array update. Data in the 45-bit shift register is trans- ferred to the parallel latches and applied to the switch array change in logic. AD8177 ...
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... AD8177 DECODER ADDRESS OUTPUT Figure 7. Logic Diagram Rev Page 06605-029 ...
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... Figure 15. RST Input (see also ESD Protection Map, Figure 19) CLK, SER/PAR, WE, 1kΩ UPDATE, SERIN A[2:0], D[4:0], CMENC, CLR DGND Figure 16. Logic Input (see also ESD Protection Map, Figure 19) 1kΩ CS 25kΩ DGND Figure 17. CS Input (see also ESD Protection Map, Figure 19) AD8177 ...
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... AD8177 VDD SEROUT DGND Figure 18. SEROUT Logic Outputs (see also ESD Protection Map, Figure 19) VPOS IPn, INn, OPn, ONn, VBLK, VOCM_CMENCOFF VOCM_CMENCON VNEG Figure 19. ESD Protection Map Rev Page VDD CLK, RST, SER/PAR, WE, UPDATE, SERIN, SEROUT, A[2:0], D[4:0], CMENC, CS, CLR ...
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... Figure 23. Small Signal Pulse Response, 200 mV p-p 1.5 1.0 0.5 0 –0.5 –1.0 –1 TIME (ns) Figure 24. Large Signal Pulse Response p OUT ERROR TIME (ns) Figure 25. Settling Time AD8177 1.2 0.8 0.4 0 –0.4 –0.8 –1 ...
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... AD8177 –1 –2 –3 –4 – TIME (ns) Figure 26. Settling Time, 1% Zoom –1 1850V/µs PEAK –2 –3 –4 – TIME (ns) Figure 27. Large Signal Rising Edge Slew Rate 0 –20 –40 –60 –80 – ...
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... Figure 35. Input Impedance 10000 1000 100 1000 1 Figure 36. Input Impedance, Single-Ended 0 –10 –20 –30 –40 –50 –60 –70 –80 1000 1 Figure 37. Output Balance Error Rev Page AD8177 10 100 1000 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) ...
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... AD8177 1.0 RED 0.5 GREEN BLUE 0 –0.5 HSYNC –1.0 –1.5 0 100 200 300 400 500 600 TIME (ns) Figure 38. Common-Mode Pulse Response 0 –10 –20 –30 –40 –50 –60 –70 –80 – FREQUENCY (MHz) Figure 39. Common-Mode Isolation, CMENC Low 200 160 120 ...
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... TIME (ns) Figure 44. Enable Time 1.2 0.025 V 0.020 OUT 1.0 0.015 0.8 0.010 0.005 0.6 0 0.4 –0.005 –0.010 0.2 –0.015 0 –0.020 –0.2 –0.025 –40 Rev Page 40ppm/°C – TEMPERATURE (°C) Figure 45. Normalized DC Gain vs. Temperature AD8177 100 ...
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... A global chip-select pin gates the input clock and the global update signal to the second rank of buffers. The AD8177 can operate on a single 5 V supply, powering both the signal path (with the VPOS/VNEG supply pins) and the control logic interface (with the VDD/DGND supply pins). ...
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... CM Middle-of-Cat-5-Run Application, CM Encoding Turned On In this application, the AD8177 is also placed somewhere in the middle of a Cat-5 run, although the common-mode handling is different. By tying CMENC high, the CM of each RGB input is passed through the part, while at the same time, the overall output CM is stripped and set equal to the voltage applied at the VOCM_ CMENCON pin ...
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... H sync is high when the CM of Blue is larger than the CM of Red. • V sync is high when the combined CM of Red and Blue is larger than the CM of Green. PROGRAMMING The AD8177 has two options for changing the programming of DIFF. R DIFF. B the crosspoint matrix. In the first option, a serial word of 45 bits CM R ...
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... WE / UPDATE cycle, significant time savings can be realized by using parallel programming. One important consideration in using parallel programming is that the RST signal does not reset all registers in the AD8177. When taken low, the RST signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time ...
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... ESD diodes (it is safest to keep the common-mode plus differential signal excursions within the supply voltages of the part). The input voltage of the AD8177 is linear for ± differential input voltage difference (this limitation is primarily due to ability of the output to swing close to the rails because the differential gain through the part is +2) ...
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... VOCM_ CMENCON or VCOM_CMENCOFF, implying a gain of +1. Likewise, sync-on common-mode signaling is carried through the AD8177 (CMENC must be in its high state), implying a gain of +1 for this path, as well. The common-mode reference pins are analog signal inputs, common to all output stages on the device ...
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... A third benefit of driving balanced loads is that the output pulse response changes as load changes. The differential signal control loop in the AD8177 forces the difference of the outputs fixed ratio to the difference of the inputs. If the two output responses are different due to loading, the control loop sees this difference as signal response error and attempts to correct this error ...
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... MAX θ example, if the AD8177 is enclosed in an environment at 45° the total on-chip dissipation under all load and A supply conditions must not be allowed to exceed 7.0 W. When calculating on-chip power dissipation necessary to include the power dissipated in the output devices due to current flowing in the loads ...
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... In fact, there are conditions where driving additional circuits in parallel in a given configuration can actually reduce the crosstalk. The fact that the AD8177 is a fully differential design means that many sources of crosstalk either destructively cancel, or are common mode to, the signal and can be rejected by a differential receiver ...
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... For example, in the case of the triple 16 × 5 matrix of the AD8177, we can look at the number of crosstalk terms that can be considered for a single channel, such as Input Channel INPUT0. INPUT0 is programmed to connect to one of the AD8177 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 15 input channels can be measured one at a time, while applying no signal to INPUT0 ...
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... Implementation of fly-by input termination often includes bringing the signal in on one routing layer, then passing through a filled via under the AD8177 input ball, then back out to termination on another signal layer. In this case, care must be taken to tie the reference ground planes together near the signal via if the signal layers are referenced to different ground planes ...
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... The designer can avoid creating stubs and reflections by keeping the AD8177 output signal path on the surface of the board. A stub is created when a top-to-bottom via connection is made on the output signal path that is perpendicular to the signal flow. ...
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... FOUR DIFFERENTIAL FOUR AD8147 RGB WITH SYNC- +2) CM CHANNELS IN0 TO IN3 OUT0 TO OUT1 IN4 TO IN7 IN8 TO IN11 DIFFERENTIAL IN12 TO IN13 OFFSET IN14 TO IN15 AD8177 DUT TWO DIFFERENTIAL RGB CHANNELS RIBBON CABLE NATIONAL INSTRUMENTS CONTROLLER BOARD USB AD8177 CUSTOMER EVALUATION BOARD GND ...
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... Rev Page CORNER INDEX AREA 1.19 DETAIL A 1.17 1.15 COPLANARITY 0.20 MAX 0.70 0.60 SEATING PLANE 0.50 BALL DIAMETER Package Option B-676 AD8177 ...
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... AD8177 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06605-0-7/07(0) Rev Page ...