ad8158 Analog Devices, Inc., ad8158 Datasheet
ad8158
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ad8158 Summary of contents
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... AD8158 can maintain link- connectivity with a pass-through connection from Port C to Port A while sending a duplicate copy of the data to test equipment on Port B. The rich feature set of the AD8158 can be controlled either through external toggle pins or by setting on-chip control 2 registers through the I C® ...
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... Voltage, and the TX_HEADROOM Bit .................................. 23 Signal Levels and Common-Mode Shift for AC-Coupled and DC-Coupled Outputs ................................................................ 24 Squelch and Disable ................................................................... 26 Speed Select ................................................................................. 26 AD8158 Power Consumption .................................................. 26 Outputs ........................................................................................ 28 Power Saving Considerations ................................................... 28 Control Interface ...................................................................... 29 Serial Interface General Functionality..................................... 29 ...
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... MAX 300 0.3 CC 590 725 820 V − − 100 110 25 150 = 1 1.6 1.8 to 3.3 3.6 2.2 3.3 3.6 1.6 1.8 to 3.3 3.6 1.2 V 1.2 V AD8158 Unit Gbps ps p p-p ps p-p ps p p Ω mV diff mV diff 0 0 ...
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... AD8158 Parameter Conditions Supply Current DC-coupled inputs/outputs, 400 mV I/O swings (800 mV p-p differential), 50 Ω far-end terminations TTO I TTI I DVCC Supply Current LB_x = all ports, dc-coupled inputs/outputs, 400 mV I/O swings (800 mV p differential), 50 Ω far-end terminations I TTO I TTI I DVCC THERMAL CHARACTERISTICS Operating Temperature Range θ ...
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... Exposure to absolute + 0 3.6V CC maximum rating conditions for extended periods may affect + 0 3.6V CC device reliability. ESD CAUTION < 0 Rev Page AD8158 ...
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... CONTROL PORT C INPUTS CONTROL 2 PIN 1 INDICATOR AD8158 12 TOP VIEW 13 (Not to Scale DIE IS PACKAGED DIE I2C PORT B OUTPUTS CONTROL Figure 3. Pin Configuration Mnemonic Type V Power EE ...
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... Input High Speed Input IN_C2 Input High Speed Input Complement IP_C2 Input High Speed Input IN_C1 Input High Speed Input Complement IP_C1 Input High Speed Input IN_C0 Input High Speed Input Complement IP_C0 Input High Speed Input Rev Page AD8158 ...
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... AD8158 Pin No 100 1 Logic level of control pins referred control pins (EQ_A0, EQ_A1, EQ_B0, EQ_B1, EQ_C0, EQ_C1) require 5 kΩ in series when DV Mnemonic Type Description 1 SEL3 Control Lane 3 A/B Switch Control SEL2 Control 1 Lane 2 A/B Switch Control 1 SEL1 Control ...
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... Figure 5. 6.5 Gbps Input Eye (TP1 from Figure 4) 50Ω CABLES 50Ω CABLES INPUT OUTPUT PIN PIN AD8158 AC-COUPLED TP1 EVALUATION BOARD Figure 4. Standard Test Circuit (No Channel) Figure 6. 6.5 Gbps Output Eye, No Channel (TP2 from Figure 4) Rev Page AD8158 2 50Ω HIGH SPEED SAMPLING TP2 OSCILLOSCOPE 25ps/DIV ...
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... Figure 10. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel (TP3 from Figure 7) Figure 11. 6.5 Gbps Output Eye, 40 Inch FR4 Input Channel (TP3 from Figure 7) Rev Page 50Ω CABLES INPUT OUTPUT PIN PIN 50Ω HIGH AD8158 SPEED AC-COUPLED TP2 TP3 SAMPLING EVALUATION OSCILLOSCOPE BOARD 25ps/DIV 25ps/DIV ...
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... TP2 EVALUATION BOARD Figure 12. Output Pre-emphasis Test Circuit Figure 15. 6.5 Gbps Output Eye, 20 Inch FR4 Input Channel Best Setting, Figure 16. 6.5 Gbps Output Eye, 30 Inch FR4 Input Channel Best Setting, Rev Page AD8158 50Ω CABLES 2 2 FR4 TEST BACKPLANE 50Ω HIGH DIFFERENTIAL ...
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... AD8158 100 DATA RATE (GHz) Figure 17. Deterministic Jitter vs. Data Rate 100 0.5 1.0 1.5 DIFFERENTIAL INPUT SWING (V p-p) Figure 18. Deterministic Jitter vs. Input Swing 100 –60 –40 – TEMPERATURE (°C) Figure 19. Deterministic Jitter vs. Temperature 6 8 2.0 2 ...
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... Figure 26. Output Amplitude (Default Setting) vs. Core Voltage OCM 1.0 0.9 0.8 0.7 0.6 0.5 0 1000 950 900 850 800 750 700 650 600 550 500 1.6 80 100 Figure 28. Propagation Delay vs. Core Supply Rev Page AD8158 1.9 2.4 2.9 3.4 CORE VOLTAGE ( RATE (Gbps) Figure 27. Output Amplitude vs. Rate 2.1 2.6 3.1 3.6 CORE SUPPLY VOLTAGE (V) 7 ...
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... AD8158 1000 950 900 850 800 750 700 650 600 550 500 –60 –40 – TEMPERATURE (°C) Figure 29. Propagation Delay vs. Temperature 140 120 100 DUT EQ SETTING Figure 30. Deterministic Jitter vs. EQ Setting ...
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... The 1:2 demux path supports bicast operation, allowing the AD8158 to operate as a port replicator as well as a redundancy switch. The AD8158 offers loopback on each lane, allowing the part to be configured as a 12-lane equalizer or redriver with FFE. ...
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... Serial control THE SWITCH (MUX/DEMUX/UNICAST/BICAST/LOOPBACK) The mux and demux functions of the AD8158 can be controlled either with the toggle pins or through the register map. The multiplexer path switches received data from Input Port A or Input Port B to Output Port C. The SEL[3:0] pins allow switching lanes independently ...
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... Rev Page AD8158 Output Port A Output Port B Output Port C Ix_C[3:0] Idle Ix_A[3:0] Idle Ix_C[3:0] Ix_B[3:0] Ix_C[3:0] Ix_C[3:0] Ix_A[3:0] Ix_C[3:0] Ix_C[3:0] Ix_B[3:0] Ix_C[3:0] Idle Ix_C[3:0] Idle Ix_C[3:0] Ix_C[3:0] Ix_C[3:0] Ix_C[3:0] ...
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... RECEIVERS The AD8158 receivers incorporate 50 Ω on-chip termination, ESD protection, and a multizero equalization function capable of delivering boost at 4.25 GHz. The AD8158 can compensate signal degradation at 6.5 Gbps from over 40 inches of FR-4 backplane trace. The receive path also incorporates a loss-of-signal (LOS) function with user programmable thresh- ...
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... Table 23). Be aware that writing to the port-level equalizer registers updates and overwrites per-lane settings. LOSS OF SIGNAL (LOS) The serial control interface allows access to the AD8158 loss of signal features. (LOS is not available in pin control mode.) Each receiver includes a low power, loss-of-signal detector. The loss- ...
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... AD8158 Table 12. Per Lane Disables Address Bit 7 Bit 6 Bit 5 0x40 0x80 0xC0 0x48 0x88 0xC8 Table 13. Port-Level EQ Setting Address Bit 7 Bit 6 Bit 5 0x41 0x81 0xC1 Table 14. Global Loss-of-Signal Squelch Control Register Address Bit 7 Bit 6 Bit 5 0x04 Table 15. Port-Level Loss-of-Signal Control Registers ...
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... Address Bit 7 Bit 6 0x44 0x84 0xC4 allowing the AD8158 to offer exceptional transmit channel compensation for legacy applications (4.5 Gbps and slower). OUTPUT LEVEL PROGRAMMING AND OUTPUT STRUCTURE The output level of the transmitter of each lane is independently programmable. In pin control mode, a default output amplitude of 800 mV p-p diff (± ...
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... AD8158 Table 19. Setting Transmitter Pre-Emphasis (Note that Toggle Pin Control Limited to the 400 mV diff Output Level Settings.) Output Level (mV diff) Pin PE_[A/B/C] Bit [A/B/C][3:0]PE[2] 200 N/A 0 200 N/A 0 200 N/A 0 200 N/A 0 200 N/A 1 200 N/A 1 200 N/A 1 300 N/A 0 300 N/A 0 300 N/A 0 300 N/A 0 300 N/A 1 300 N/A 1 300 N/A 1 400 0 0 400 ...
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... With the pre-emphasis configured for 4.25 Gbps operation (SEL4G = 1), the overshoot can only be reduced 5% from the theoretic maximum. In this case, the peak minimum voltage limit should be more closely observed. Rev Page AD8158 = V peak because transmitter pre-emphasis is L satisfies the minimum limit of 2 ...
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... AD8158 SIGNAL LEVELS AND COMMON-MODE SHIFT FOR AC-COUPLED AND DC-COUPLED OUTPUTS Table 20. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting Output Levels and Output Compliance TOT PRED D_PEAK (mV) (mA) (mA) (mV) Boost (dB) V and V = 3.3 V TTO ...
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... Maximum single-ended output voltage OD /2 Minimum single-ended output voltage OD DV OCM p × Figure 40 OCM Rev Page TX_HEADROOM = 0 TX_HEADROOM = Peak Peak H L (V) (V) (V) Min V (V) L 1.2 1.8 1.2 0.7 1.1 0.7 1.1 1.8 1 0.7 0.9 0.7 1 1.8 0.8 0.7 0.7 0.7 0.7 V TTO OCM AD8158 Min V (V) L 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ...
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... AD8158 POWER CONSUMPTION There are several sections of the AD8158 that draw varying power depending on the supply voltages, the type of I/O coupling used, and the status of the AD8158 operation. Figure 41 , but there TTO shows a block diagram of these sections. Figure 42 summarizes the power consumption of each section and is a useful guide as the following sections are reviewed ...
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... Figure 42. Power Budget Calculator Rev Page AD8158 06646-033 ...
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... AD8158 output circuit and out through V The power dissipated in the transmission line and the destination resistor is not dissipated in the AD8158 but has to be supplied from the power supply and is a factor in the overall system power. The current in the on-chip termination resistors and the output current source dissipate power in the AD8158 itself ...
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... In Figure 43, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I master and never by the AD8158 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8158, whereas the data in the nonshaded polygons is driven by the I The end phase case shown is that of Step 9A ...
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... The address pins are set to b011. In Figure 44, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I by the AD8158 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8158, whereas the data in the nonshaded polygons is driven by the I case shown is that of Step 13A ...
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... V TTI TTO SINGLE SUPPLY vs. MULTIPLE SUPPLY OPERATION The AD8158 supports a flexible supply voltage of 1 3.3 V. For some dc-coupled links, 1 ground-referenced signaling may be desired. In these cases, the AD8158 can be run with a split supply configuration. Table 22. Alternate Supply Configuration Examples Signal Level 1.2 V CML GND − ...
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... AD8158 REGISTER MAP All registers are port-level and global registers, unless otherwise noted. Table 23. Register Definitions Mnemonic Addr. Bit 7 Bit 6 Reset 0x00 Switch 0x01 LBC Control 1 Switch 0x02 Control 2 Global 0x04 Squelch Ctrl Switch Core/ 0x05 TX_HEAD Headroom ROOM_C Mode 0x0F ...
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... C3EQ[0] C2EQ[3] PNC3 LOSC1 LOSC0 LOSC3 Active Sticky Sticky TXDIS C3 CLEV[1] CLEV[0] C1PE[1] C1PE[0] C3PE[1] C3PE[0] C2OLEV[1] C2OLEV[0] C1OLEV[1] Rev Page AD8158 Bit 2 Bit 1 Bit 0 B2PE[2] B2PE[1] B2PE[0] B1OLEV[0] B0OLEV[1] B0OLEV[0] RXDIS C2 RXDIS C1 RXDIS C0 CEQ[2] CEQ[1] CEQ[0] THRBIT[2] THRBIT[1] THRBIT[0] ...
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... AD8158 OUTLINE DIMENSIONS 12.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range AD8158ACPZ 1 −40°C to +85°C 1 AD8158-EVALZ RoHS Compliant Part. 0.60 MAX 0.60 MAX 75 76 0.40 BSC 11.75 BSC 0.50 0.40 0.70 0.30 0.65 0.60 0.05 MAX 0.01 NOM 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VRRE. Figure 45. 100-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...
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... NOTES Rev Page AD8158 ...
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... AD8158 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...