ad8105 Analog Devices, Inc., ad8105 Datasheet
ad8105
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ad8105 Summary of contents
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... VNEG VOCM **AD8105 ONLY Figure 1. while the AD8105 has a differential gain of +2 for ease of use in back-terminated load applications. They operate as fully differential devices or can be configured for single-ended operation. Either a single +5 V supply or dual ±2.5 V supplies can be used, while consuming only 340 mA of idle current with all outputs enabled ...
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... AD8104/AD8105 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics (Serial Mode) ....................................... 5 Timing Characteristics (Parallel Mode) .................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 Power Dissipation......................................................................... 7 REVISION HISTORY 6/07—Revision 0: Initial Version ESD Caution...................................................................................7 Pin Configuration and Function Descriptions..............................8 Truth Table and Logic Diagram ............................................... 13 I/O Schematics ...
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... V Input Impedance OCM = 0 V, differential I/O mode, unless otherwise noted. OCM = 150 Ω 150 Ω p-p OUT, diff = 2.8 V p-p OUT, diff = 2 V p-p IN, diff Rev Page AD8104/AD8105 AD8104/AD8105 Min Typ Max 600 420/525 100/50 70/50 1.3 2.5 1800 1500 0.05 0.05 −80/−70 −72/−68 −48/−50 −40/−50 − ...
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... VDD, outputs enabled, no load Supply Voltage Range PSRR VNEG, VPOS MHz VOCM MHz OPERATING TEMPERATURE RANGE Temperature Range Operating (still air) θ Operating (still air) JA θ Operating (still air) JC AD8104/AD8105 Min Typ 100 100 40 340 210 340 210 4 −40 to +85 ...
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... OUT15 (D4 Figure 2. Timing Diagram, Serial Mode DATA OUT RESET , SER/PAR, CLK, DATA IN, UPDATE DGND + 1 μA max 0.5 V max Rev Page AD8104/AD8105 Limit Min Typ Max 150 10 90 120 100 60 200 OUT0 (D0 TRANSFER DATA FROM SERIAL ...
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... AD8104/AD8105 TIMING CHARACTERISTICS (PARALLEL MODE) Specifications subject to change without notice. Table 4. Parameter Parallel Data Setup Time WE Pulse Width Parallel Data Hold Time WE Pulse Separation WE to UPDATE Delay UPDATE Pulse Width Propagation Delay, UPDATE to Switch On or Off RESET Pulse Width RESET Time ...
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... BGA 14 1 6.5 POWER DISSIPATION The AD8104/AD8105 are operated with ±2 supplies and can drive loads down to 100 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken derating the operating conditions based on ambient temperature. ...
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... VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG AD8104/AD8105 BOTTOM VIEW (Not to Scale) VNEG VNEG VNEG VPOS VPOS VPOS VNEG VNEG VNEG VNEG VPOS VPOS VPOS VNEG OP12 ON10 OP10 ON8 OP8 ...
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... ON9 Figure 6. Package Top View Ball No. A15 A16 A17 A18 A19 A20 A21 A22 A23 Rev Page AD8104/AD8105 VPOS VPOS VPOS VPOS VPOS VNEG VNEG ...
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... AD8104/AD8105 Ball No. Mnemonic Description Connect Connect Connect Connect. B10 NC No Connect. B11 NC No Connect. B12 NC No Connect. B13 NC No Connect. B14 NC No Connect. B15 NC No Connect. B16 NC No Connect. B17 NC No Connect. B18 NC No Connect. B19 NC No Connect. ...
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... Analog Positive Power Supply. Y13 VPOS Analog Positive Power Supply. Y14 VNEG Analog Negative Power Supply. Y15 VNEG Analog Negative Power Supply. Y16 VNEG Analog Negative Power Supply. Y17 VNEG Analog Negative Power Supply. Y18 VNEG Analog Negative Power Supply. Rev Page AD8104/AD8105 ...
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... AD8104/AD8105 Ball No. Mnemonic Description Y19 VOCM Output Common-Mode Reference Supply. Y20 VNEG Analog Negative Power Supply. Y21 VPOS Analog Positive Power Supply. Y22 IP31 Input Number 31, Positive Phase. Y23 VPOS Analog Positive Power Supply. AA1 VPOS Analog Positive Power Supply. AA2 VPOS Analog Positive Power Supply ...
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... X N parallel mode Rev Page AD8104/AD8105 SER/PAR Operation/Comment X Asynchronous reset. All outputs are disabled. Remainder of logic in 192-bit shift register is unchanged. 0 Serial mode. The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 192 clock cycles later ...
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... AD8104/AD8105 DECODER ADDRESS OUTPUT Figure 7. Logic Diagram Rev Page 06612-007 ...
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... Figure 10. AD8104 Receiver (see also ESD Protection Map, Figure 18) 2500Ω IPn 1.3pF 0.3pF 1.3pF INn 2500Ω Figure 11. AD8105 Receiver (see also ESD Protection Map, Figure 18) Figure 12. AD8104/AD8105 Receiver Simplified Equivalent Circuit When OPn 3.4pF 3.4pF ONn Figure 13. AD8104/AD8105 Receiver Simplified Equivalent Circuit When 2538Ω ...
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... AD8104/AD8105 CLK, SER/PAR, WE, 1kΩ UPDATE, DATA IN, A[3:0], D[5:0] Figure 16. Logic Input (see also ESD Protection Map, Figure 18) VDD DATA OUT DGND Figure 17. Logic Output (see also ESD Protection Map, Figure 18) OPn, ONn, DGND Rev Page VPOS VDD CLK, RESET, SER/PAR, WE, ...
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... diff –2 –4 –6 –8 – FREQUENCY (MHz) Figure 19. AD8104, AD8105 Small Signal Frequency Response, 200 mV p –2 –4 –6 –8 – FREQUENCY (MHz) Figure 20. AD8104, AD8105 Large Signal Frequency Response p ...
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... AD8105 80 60 AD8104 10k FREQUENCY (Hz) Figure 27. AD8104, AD8105 Noise Spectral Density, RTO VOCM AGGRESSOR 100 1000 100 1000 DIFFERENTIAL OUT 100k 1M Figure 30. AD8104 Crosstalk, One Adjacent Channel, Single-Ended Rev Page DIFFERENTIAL IN/OUT –20 – ...
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... SINGLE-ENDED IN/OUT –20 –40 –60 –80 –100 300k 1M 10M 100M FREQUENCY (Hz) Figure 31. AD8105 Crosstalk, One Adjacent Channel, Single-Ended 0 DIFFERENTIAL IN/OUT –20 –40 –60 –80 –100 –120 300k 1M 10M 100M FREQUENCY (Hz) Figure 32. AD8104 Crosstalk, All Hostile 0 DIFFERENTIAL IN/OUT –20 –40 –60 –80 – ...
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... DIFFERENTIAL IN 100M 1G SINGLE-ENDED IN 100M 1G Rev Page 30000 DIFFERENTIAL OUT 25000 20000 15000 10000 5000 0 100k 1M 10M 100M FREQUENCY (Hz) Figure 40. AD8104, AD8105 Output Impedance, Disabled 1000 100 10 1 0.1 100k 1M 10M 100M FREQUENCY (Hz) Figure 41. AD8104, AD8105 Output Impedance, Enabled 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 – ...
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... Rev Page AD8104/AD8105 UPDATE 0 V OUT –40 – TIME (ns) Figure 46. AD8104 Switching Time V OUT SLEW RATE TIME (ns) Figure 47. AD8104 Large Signal Rising Edge and Slew Rate ...
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... AD8104/AD8105 –40 –30 –20 – TEMPERATURE (ºC) Figure 49. AD8104 V vs. Temperature with All Outputs Enabled –10 –20 –0.10 –0.08 –0.06 –0.04 –0.02 0 0.02 TIME (µs) Figure 50. AD8104 Switching Transient (Glitch) 0.020 0.015 0.010 0.005 0 – ...
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... Figure 58. AD8104, AD8105 Quiescent Supply Currents vs. Temperature 2.8 360 2.4 340 2.0 320 1.6 300 1.2 280 0.8 260 0.4 240 0 220 –0.4 200 1 110 130 150 Figure 59. AD8104, AD8105 Quiescent Supply Currents vs. Enabled Outputs –5 75 100 0 Rev Page AD8104/AD8105 I (SERIAL MODE) ...
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... Rev Page OUTP V INP 0 V OUTN V INN 0 100 200 300 400 500 TIME (ns) Figure 63. AD8105 Overdrive Recovery, Single-Ended p-p, DIFF OUT THIRD HARMONIC SECOND HARMONIC 0 100 FREQUENCY (MHz) Figure 64. AD8104 Harmonic Distortion 600 7 00 1000 ...
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... A mask-programmable feedback network sets the closed-loop differential gain. For the AD8104, this differential gain is +1, and for the AD8105, this differential gain is +2. The receiver has an input stage that does not respond to the common mode of the signal. This architecture, along with the attenuating feedback network, allows the user to apply input voltages that extend from rail to rail ...
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... One important consideration in using parallel programming is that the RESET signal does not reset all registers in the AD8104/ AD8105. When taken low, the RESET signal only sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time. ...
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... where 2.5 kΩ the user single-ended source resistance (such as 37.5 Ω for S a back-terminated 75 Ω source 2.538 kΩ for the AD8104 and 5.075 kΩ for the AD8105 the case of the AD8104 538 kΩ kΩ the case of the AD8105, ...
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... S a back-terminated 75 Ω source 2.538 kΩ for the AD8104 and 5.075 kΩ for the AD8105 most cases, a single-ended input signal is referred to midsup- ply, typically ground. In this case, the undriven differential input can be connected to ground. For best dynamic performance and ...
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... Table 1. Regardless of the differential gain of the device, the common- mode gain for the AD8104 and AD8105 the output. This means that the common mode of the output voltages directly follows the reference voltage applied to the VOCM input. ...
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... The differential signal control loop in the AD8104/ AD8105 forces the difference of the outputs fixed ratio to the difference of the inputs. If the two output responses are different due to loading, this creates a difference that the control loop sees as signal response error, and it attempts to correct this error ...
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... MAX θ example, if the AD8104/AD8105 is enclosed in an envi- ronment at 45° the total on-chip dissipation under all A load and supply conditions must not be allowed to exceed 7.0 W. When calculating on-chip power dissipation necessary to include the rms current being delivered to the load, multiplied by the rms voltage drop on the AD8104/AD8105 output devices ...
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... When there are many signals in close proximity in a system undoubtedly the case in a system that uses the AD8104/AD8105, the crosstalk issues can be quite complex. A good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system that uses one or more crosspoint devices ...
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... If a larger crosspoint array of multiple AD8104/AD8105s is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. One common method is to measure all-hostile crosstalk ...
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... AD8104/AD8105 input should be placed no farther than 1.5 cm after the termination resistors, and preferably should be placed even closer. The BGA substrate routing inside the AD8104/ AD8105 is approximately length and adds to the stub length, so 1.5 cm PCB routing equates 2.5 × 10 calculations. where …}. ...
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... If multiple AD8104/AD8105s are to be driven in parallel, a fly- by input termination scheme is very useful, but the distance from each AD8104/AD8105 input to the driven input transmis- sion line is a stub that should be minimized in length and parasitics using the discussed guidelines. When driving the AD8104/AD8105 single-endedly, the undriven input is often terminated with a resistance to balance the input stage ...
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... ORDERING GUIDE Model Temperature Range 1 AD8104ABPZ −40°C to +85°C 1 AD8105ABPZ −40°C to +85°C AD8104-EVAL AD8105-EVAL RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...