mc13176d ETC-unknow, mc13176d Datasheet - Page 8

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mc13176d

Manufacturer Part Number
mc13176d
Description
Fm/am Transmitter
Manufacturer
ETC-unknow
Datasheet

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0
dthus, R 2 = t 2 /C = 0.283
In the above example, the following standard value
components are used,
(R 1 is defined as R 1 – 53 k, the output impedance of the
phase detector.)
(~50 k) and serves as a current source, and the input to the
frequency control, Pin 6 is low impedance (impedance of the
two diode to ground is approximately 500 ), it is imperative
that the second order low pass filter design above be
modified. In order to minimize loading of the R 2 C shunt
network, a higher impedance must be established to Pin 6. A
simple solution is achieved by adding a low pass network
between the passive second order network and the input to
Pin 6. This helps to minimize the loading effects on the
second order low pass while further suppressing the
sideband spurs of the crystal oscillator. A low pass filter with
R 3 = 1.0 k and C 2 = 1500 p has a corner frequency (f c ) of
106 kHz; the reference sideband spurs are down greater
than – 60 dBc.
Hold–In Range
range and synchronization range, is the ability of the CCO
frequency, f o to track the input reference signal, f ref N as it
gradually shifted away from the free running frequency, f f .
Assuming that the CCO is capable of sufficient frequency
deviation and that the internal loop amplifier and filter are not
overdriven, the CCO will track until the phase error,
approaches
8
then, R 1 = t 1 /C = 33.8
Since the output of the phase detector is high impedance
The hold–in range, also called the lock range, tracking
For C = 0.47 ;
C = 0.47 ; R 2 = 620 and R 1 = 72 k – 53 k ~ 18 k
Pin 7
Figure 14. Modified Low Pass Loop Filter
18k
R 1
Detector
Output
/2 radians. Figures 5 through 8 are a direct
Phase
0.47
620
30 A
30 A


R 2
C
10 –3 /0.47
10 –3 /0.47
1.0k
R 3
V CC
7
C 3
C 1


1500p
10 –6 = 72 k
10 –6 = 0.60 k
1000p
Pin 6
Figure 15. External Loop Amplifier
R 1
R 2
MC13175 MC13176
68k
33k
V CC = 3.0Vdc
R 3
e
2N4402
4.7k
1.0k
R 4
measurement of the hold–in range (i.e. f ref
2 ). Since sin e cannot exceed 1.0, as e approaches
the hold–in range is equal to the DC loop gain, K v
In the above example,
Extended Hold–in Range
over temperature in cases where the free–running oscillator
drifts more than 2 to 3% because of relatively high
temperature coefficients of the ferrite tuned CCO inductor.
This problem might worsen for lower frequency applications
where the external tuning coil is large compared to internal
capacitance at Pins 1 and 4. To improve hold–in range
performance, it is apparent that the gain factors involved
must be carefully considered.
(R 5 ) of 15 k to V CC (3.0 Vdc) provides approximately 100 A
of current boost to supplement the existing 50 A internal
source current. R 4 (1.0 k) is selected for approximately
0.1 Vdc across it with 100 A. R 1 , R 2 and R 3 are selected to
set the potential at Pin 7 and the base of 2N4402 at
approximately 0.9 Vdc and the emitter at 1.55 Vdc when error
current to Pin 6 is approximately zero A. C 1 is chosen to
reduce the level of the crystal sidebands.
The hold–in range of about 3.4% could cause problems
In the design example in Figure 15, an external resistor
K n = is either 1/8 in the MC13175 or 1/32 in the
K n =
K p = is fixed internally and cannot be altered.
K o = Figures 9 and 10 suggest that there is capability
K o =
K o =
K o =
K o =
K o =
K o =
Ka = External loop amplification will be necessary
Ka =
R 5
5, 10, 15
MC13176.
of greater control range with more current swing.
However, this swing must be symmetrical about
the center of the dynamic response. The
suggested zero current operating point for
offset point.
since the phase detector only supplies
1.6V
15k
100 A swing of the CCO is at about + 70 A
12
where, K v = K p K o K n.
6
f H =
H =
H =
50 A
MOTOROLA RF/IF DEVICE DATA
4.35 MHz
K v
27.3 Mrad/sec

N
Oscillator
Circuitry
Control

N =

30 A.
N.
f H

/2