sx1506i089trt Semtech Corporation, sx1506i089trt Datasheet - Page 22

• Manufacturer Part Number: sx1506i089trt
• Description: Sx1504/sx1505/sx1506 4/8/16 Channel Gpio With Nint And Nreset
• Manufacturer: Semtech Corporation

Addr
Addr
0x15
0x00
0x01
0x02
ADVANCED COMMUNICATIONS & SENSING
5.3
*Bits set as output take “1” as default value.
Rev 1 – 3
Address
0xAD
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x2A
0x2B
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x10
0x11
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
Name
RegPLDTable4
Name
RegDataB
RegDataA
RegDirB
SX1506 16-channel GPIO
rd
Oct. 2008
Name
RegDataB
RegDataA
RegDirB
RegDirA
RegPullUpB
RegPullUpA
RegPullDownB
RegPullDownA
RegInterruptMaskB
RegInterruptMaskA
RegSenseHighB
RegSenseHighA
RegSenseLowB
RegSenseLowA
RegInterruptSourceB
RegInterruptSourceA
RegEventStatusB
RegEventStatusA
RegPLDModeB
RegPLDModeA
RegPLDTable0B
RegPLDTable0A
RegPLDTable1B
RegPLDTable1A
RegPLDTable2B
RegPLDTable2A
RegPLDTable3B
RegPLDTable3A
RegPLDTable4B
RegPLDTable4A
RegAdvanced
Default
Default
Table 14 – SX1505 Configuration Registers Description
0xFF
0xFF
0xFF
0x00
Table 15 – SX1506 Configuration Registers Overview
Bits
Bits
7:0
7:0
7:0
4
3
2
1
0
7
6
5
4
3
2
1
0
Description
Data register for Bank B I/O[15:8]
Data register for Bank A I/O[7:0]
Direction register for Bank B I/O[15:8]
Direction register for Bank A I/O[7:0]
Pull-up register for Bank B I/O[15:8]
Pull-up register for Bank A I/O[7:0]
Pull-down register for Bank B I/O[15:8]
Pull-down register for Bank A I/O[7:0]
Interrupt mask register for Bank B I/O[15:8]
Interrupt mask register for Bank A I/O[7:0]
Sense register for I/O[15:12]
Sense register for I/O[7:4]
Sense register for I/O[11:8]
Sense register for I/O[3:0]
Interrupt source register for Bank B I/O[15:8]
Interrupt source register for Bank A I/O[7:0]
Event status register for Bank B I/O[15:8]
Event status register for Bank A I/O[7:0]
PLD mode register for Bank B I/O[15:8]
PLD mode register for Bank A I/O[7:0]
PLD truth table 0 for Bank B I/O[15:8]
PLD truth table 0 for Bank A I/O[7:0]
PLD truth table 1 for Bank B I/O[15:8]
PLD truth table 1 for Bank A I/O[7:0]
PLD truth table 2 for Bank B I/O[15:8]
PLD truth table 2 for Bank A I/O[7:0]
PLD truth table 3 for Bank B I/O[15:8]
PLD truth table 3 for Bank A I/O[7:0]
PLD truth table 4 for Bank B I/O[15:8]
PLD truth table 4 for Bank A I/O[7:0]
Advanced settings register
Description
Value to be output on I/O[4] when I/O[2:0] = 100
Value to be output on I/O[4] when I/O[2:0] = 011
Value to be output on I/O[4] when I/O[2:0] = 010
Value to be output on I/O[4] when I/O[2:0] = 001
Value to be output on I/O[4] when I/O[2:0] = 000
Value to be output on I/O[3] when I/O[2:0] = 111
Value to be output on I/O[3] when I/O[2:0] = 110
Value to be output on I/O[3] when I/O[2:0] = 101
Value to be output on I/O[3] when I/O[2:0] = 100
Value to be output on I/O[3] when I/O[2:0] = 011
Value to be output on I/O[3] when I/O[2:0] = 010
Value to be output on I/O[3] when I/O[2:0] = 001
Value to be output on I/O[3] when I/O[2:0] = 000
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
Write: Data to be output to the output-configured IOs
Read: Data seen at the IOs, independent of the direction configured.
Configures direction for each IO.
0 : IO is configured as an output
1 : IO is configured as an input
22
Description
SX1504/SX1505/SX1506
4/8/16 Channel GPIO
Applies only when
PLDModeLow is set to PLD 3-
to-2 mode
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1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Default
*
*