at42qt1070 ATMEL Corporation, at42qt1070 Datasheet
at42qt1070
Available stocks
Related parts for at42qt1070
at42qt1070 Summary of contents
Page 1
... SOIC RoHS compliant IC – 20-pin VQFN RoHS compliant IC • Signal Processing: – Self-calibration – Auto drift compensation – Noise filtering ® – Adjacent Key Suppression ® (AKS – three groups possible) QTouch 7-channel Sensor IC AT42QT1070 2 C-compatible 9596A–AT42–10/10 ...
Page 2
... Pinouts and Schematics 1.1 Pinout Configuration – Comms Mode (14-pin SOIC) 1.2 Pinout Configuration – Standalone Mode (14-pin SOIC) MODE (Vdd) AT42QT1070 2 1 Vdd MODE (Vss) 2 QT1070 3 SDA 4 RESET 5 CHANGE SCL 6 KEY6 7 1 Vdd 2 QT1070 3 OUT0 4 RESET 5 OUT4 OUT3 6 OUT2 7 14 Vss 13 KEY0 ...
Page 3
... KEY3 KEY2 KEY1 KEY0 9596A–AT42–10/ QT1070 QT1070 AT42QT1070 SCL CHANGE RESET SDA MODE (Vss) OUT3 OUT4 RESET OUT0 MODE (Vdd) 3 ...
Page 4
... KEY4 10 KEY3 KEY3 11 KEY2 KEY2 12 KEY1 KEY1 13 KEY0 KEY0 14 Vss AT42QT1070 4 Type Description Vdd P Power Mode selection pin I Comms Mode – connect to Vss Standalone Mode – connect to Vdd Comms Mode – Standalone Mode – open drain output for guard channel I RESET – ...
Page 5
... Standalone Mode – connect to output N/C – Not connected N/C – Not connected N/C – Not connected I Input only O Output only, push-pull OD Open drain output P Ground or power AT42QT1070 If Unused, Connect To... 2 C-compatible data line 2 C-compatible clock Open Open Open Open Open – – – – – – ...
Page 6
... SDA CHANGE RESET Figure 1-2. Typical Circuit – Standalone (14-pin SOIC) OUTPUTS C and are optional OUT0 4 C OUT0 C OUT4 Vdd R OUT0 Vss R1 R OUT4 RESET AT42QT1070 6 Vdd C1 Vdd 1 Vss R Vdd SCL 6 SCL QT1070 Rs6 KEY6 7 R RST Rs5 KEY5 8 Rs4 3 KEY4 9 SDA ...
Page 7
... The central pad on the underside of the chip is a Vss pin 19 and should be connected to ground. Do not put any other N/C 20 tracks underneath the body of the chip. N important to place all Rs components physically near Vss to the chip. 8 Vss AT42QT1070 OUTPUTS C and are optional OUT1 2 ...
Page 8
... Section 3.1 on page standalone mode) • Section 3.2 on page • Section 3.4 on page • Section 4.4 on page AT42QT1070 8 1-1, 1-2, 1-3 and 1-4, check the following sections for component values: 13: Series resistors (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for 13: LED traces 14: Power Supply (voltage levels) 17: SDA, SCL pull-up resistors 9596A– ...
Page 9
... Overview 2.1 Introduction The AT42QT1070 (QT1070 digital burst mode charge-transfer (QT driver. The device can sense from one to seven keys, dependent on mode. The QT1070 includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation and no external Cs capacitors are required ...
Page 10
... QT1070 can sleep for as long as possible. Communications wake up the QT1070 from sleep causing a higher power consumption if the part is randomly polled. Note: AT42QT1070 10 22) which can be written to via I The CHANGE line is pulled low 100 ms after power-up or reset. ...
Page 11
... A calibrate command clears all key status bits and the overflow bit (until it is checked on the next cycle). Section 5.9 on page 21) than the other keys. In standalone mode it should have an Averaging Factor of 16 AT42QT1070 for information about design guidelines. 21) and a lower Threshold (see Section 5.8 ...
Page 12
... DI filter is 2. Settings of 0 and 1 for the DI also default to 2. The DI is also implemented when a touch is removed. 2.12.3 Cx Limitations The recommended range for key capacitance – 30 pF. Larger values of Cx will give reduced sensitivity. AT42QT1070 12 Guard Channel Example Section 5.10 on page 2 C-compatible commands. ...
Page 13
... If bit 4 of address 53 is clear then a recalibration of all keys occurs on Max On Duration instead of the individual key recalibration. AT42QT1070 13 ...
Page 14
... To assist with transient regulator stability problems, the QT1070 waits 500 µs any time it wakes up from a sleep state (in LP modes) before acquiring, to allow Vdd to fully stabilize. AT42QT1070 PCB is reworked in any way almost guaranteed that the behavior CAUTION: of the no-clean flux will change ...
Page 15
... C-compatible address of 0x1B. This is not changeable. Host to Device MemAddress S SLA+W A Description of Write Data Bits Description START condition Slave address plus write bit Acknowledge bit Target memory address within device Data to be written Stop condition AT42QT1070 Table 5-1 on Device to Host Data ...
Page 16
... If the host returns a NACK, it should then terminate the transfer by issuing the 9. The device resets the internal address to the location indicated by the memory address sent to it previously. Therefore, there is no need to send the memory address again when reading from the same location. Note: AT42QT1070 16 Host to Device S SLA+W ...
Page 17
... C-compatible master and slave devices can only drive these lines low or 2 C-compatible specifications (1 µs maximum). 2 C-compatible communications are not required, then standalone mode AT42QT1070 2 C-compatible device is and should be chosen so that the Section 2.4 on page 9 for more 17 ...
Page 18
... NTHR key 4 37 NTHR key 5 38 NTHR key 6 39 AVE/AKS key 0 40 AVE/AKS key 1 41 AVE/AKS key 2 42 AVE/AKS key 3 AT42QT1070 18 2 C-compatible serial interfaces. In standalone these settings are fixed to Bit 6 Bit 5 Bit 4 Bit 3 Major Firmware version number – – – ...
Page 19
... Detection integrator counter for key 5 Detection integrator counter for key 6 FastOutDI/ Max Cal/Guard Channel Low Power (LP) Mode Maximum On Duration Calibrate RESET Chip MAJOR ID Firmware Version FIRMWARE VERSION AT42QT1070 Bit 3 Bit 2 Bit 1 Bit MINOR R/W R/W R/W R/W R/W R/W R/W ...
Page 20
... REFERENCE DATA: addresses 18 – 31 allow reference data to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored MSByte first. These addresses are read-only. AT42QT1070 20 Detection Status ...
Page 21
... NEGATIVE THRESHOLD FOR KEYS 0 – not use a setting this causes a key to go into detection when its signal is equal to its reference. AVE/AKS AVE5 AVE4 AVE3 Detection Integrator DETECTION INTEGRATOR AT42QT1070 AVE2 AVE1 AVE0 AKS1 b4 b3 ...
Page 22
... LP MODE: this 8-bit value determines the number intervals between key measurements. Longer intervals between measurements yield a lower power consumption but at the expense of a slower response to touch. Setting ...254 255 Default: 2 (16 ms between key acquisitions) AT42QT1070 22 Max On/Guard Channel – FO MAX CAL LP Mode b7 ...
Page 23
... Writing any nonzero value to this address triggers the device to reset. 9596A–AT42–10/10 Max Time MAX ON DURATION Time Off 160 ms 320 ms 480 ms 640 ms 40.8s Calibrate Writing a nonzero value forces a calibration RESET Writing a nonzero value forces a reset AT42QT1070 ...
Page 24
... Vdd = 3.3V 10nF, load = 5 pF default sleep recommended range, unless otherwise noted Parameter Description Vil Low input logic level Vih High input logic level Vol Low output voltage Voh High output voltage Iil Input leakage current AT42QT1070 24 -0.5 to +6V ±10 mA infinite infinite -0.5V to (Vdd + 0.5) Volts o - + +125 +1.8V to 5.5V ± ...
Page 25
... DI setting LP mode + (DI setting x – ms) 162 180 198 – <230 – – – 400 ±8 5 – – AT42QT1070 1.8V 442 305 261 234 221 211 Units Notes ms Under host control Modulated kHz spread-spectrum (chirp) Can be longer if burst is ms very long. kHz – ...
Page 26
... Mechanical Dimensions 6.7 AT42QT1070X-SSU – 14-pin SOIC Top View Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006" ...
Page 27
... AT42QT1070X-MMH – 20-pin VQFN Pin TOP VIEW Pin #1 Chamfer BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com 9596A–AT42–10/ C0.18 (8X 0. 0.3 Ref (4x) K TITLE 20M2, 20-pad 0.85 mm Body, Lead Pitch 0.45 mm, 1 ...
Page 28
... Marking 6.9.1 AT42QT1070-SSU – 14-pin SOIC Either part marking can be used. AT42QT1070 28 1070 1R5 Pin 1 ID Code revision 1.5, released 1 Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52 ATMEL QT1070 1R5 YYWW Pin 1 ID Code revision 1.5, released 1 Abbreviated ...
Page 29
... AT42QT1070-MMH – 20-pin VQFN Either part marking can be used. 9596A–AT42–10/10 Pin 1 ID 42E Code Revision 1.5, 15 released Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52 Pin 1 ID 170 15X 15 = Code Revision 1.5, released YZZ ...
Page 30
... Part Number Part Number AT42QT1070-SSU AT42QT1070-MMH 6.11 Moisture Sensitivity Level (MSL) AT42QT1070 30 Description 14-pin SOIC RoHS compliant IC 20-pin VQFN RoHS compliant IC MSL Rating Peak Body Temperature MSL3 260 Specifications o C IPC/JEDEC J-STD-020 9596A–AT42–10/10 ...
Page 31
... Device 1 Device 2 SDA SCL Data Transfer SDA SCL Data Stable A-3, START and STOP conditions are signaled by changing the level of the SDA line AT42QT1070 2 C-compatible bus. The following sections give Figure A-1. Both bus lines are connected 2 C-compatible devices must be open-drain Vdd Device 3 ...
Page 32
... START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signaled. AT42QT1070 32 START and STOP Conditions SDA ...
Page 33
... Data Byte Format Data MSB 1 2 SLA+R/W shows a typical data transmission. Note that several data bytes can be transmitted Addr LSB R/W ACK Data MSB AT42QT1070 Data LSB ACK Data Byte Data LSB ACK Data Byte ...
Page 34
... Contents Features ..................................................................................................... 1 1 Pinouts and Schematics ......................................................................... 2 2 Overview ................................................................................................... 9 AT42QT1070 34 1.1 Pinout Configuration – Comms Mode (14-pin SOIC) .........................................2 1.2 Pinout Configuration – Standalone Mode (14-pin SOIC)....................................2 1.3 Pinout Configuration – Comms Mode (20-pin VQFN) ........................................3 1.4 Pinout Configuration – Standalone Mode (20-pin VQFN) ..................................3 1.5 Pin Descriptions..................................................................................................4 1.6 Schematics .........................................................................................................6 2.1 Introduction.........................................................................................................9 2 ...
Page 35
... Address 32 – 38: Negative Threshold (NTHR).................................................21 5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS) ....21 5.10 Address 46 – 52: Detection Integrator (DI).......................................................21 5.11 Address 53: FastOutDI/Max Cal/Guard Channel .............................................22 5.12 Address 54: Low Power (LP) Mode..................................................................22 5.13 Address 55: Max On Duration ..........................................................................23 5.14 Address 56: Calibrate .......................................................................................23 5.15 Address 57: RESET .........................................................................................23 6.1 Absolute Maximum Specifications....................................................................24 6.2 Recommended Operating Conditions ..............................................................24 6.3 DC Specifications .............................................................................................24 6.4 Power Consumption Measurements ................................................................25 AT42QT1070 35 ...
Page 36
... Timing Specifications........................................................................................25 6.6 Mechanical Dimensions....................................................................................26 6.7 AT42QT1070X-SSU – 14-pin SOIC .................................................................26 6.8 AT42QT1070X-MMH – 20-pin VQFN ...............................................27 6.9 Marking.............................................................................................................28 6.9.1 AT42QT1070-SSU – 14-pin SOIC.............................................. 28 6.9.2 AT42QT1070-MMH – 20-pin VQFN............................ 29 6.10 Part Number .....................................................................................................30 6.11 Moisture Sensitivity Level (MSL) ......................................................................30 I2C-compatible Operation................................................. 31 A.1 Interface Bus ....................................................................................................31 A.2 Transferring Data Bits.......................................................................................31 A.3 START and STOP Conditions ..........................................................................31 A ...
Page 37
... Associated Documents • QTAN0062 – QTouch and QMatrix Sensitivity Tuning for Keys, Slider and Wheels • Touch Sensors Design Guide Revision History Revision Number Revision A – October 2010 9596A–AT42–10/10 History Initial release of document for code revision 1.5 AT42QT1070 37 ...
Page 38
... Technical Support www.atmel.com touch@atmel.com Literature Requests www.atmel.com/literature ® , Atmel logo and combinations thereof, Adjacent Key Suppression ™ and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) 3-3523-3551 Fax: (+81) 3-3523-7581 Sales Contact www ...