at42qt1481 ATMEL Corporation, at42qt1481 Datasheet
at42qt1481
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at42qt1481 Summary of contents
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... TQFP RoHS compliant • Signal processing: – Self-calibration, auto drift compensation, noise filtering, Adjacent Key ® Suppression • Patents: – Adjacent Key Suppression (AKS ® – QMatrix (patented charge-transfer method) technology ® ) technology 48-key QMatrix IC AT42QT1481 9621B–AT42–06/11 ...
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... MISO 1.2 Pin Descriptions Table 1-1. Pin Listing Pin Name 1 MOSI 2 MISO 3 SCK 4 RST 5 Vdd 6 Vss 7 XT2 8 XT1 AT42QT1481 SCK 3 RST 4 Vdd 5 QT1481 Vss 6 XT2 7 XT1 ...
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... This pin MUST be used comms ready; need a 20 µs grace period before I/O checking. Open-drain with internal 20 k – 50 k pull-up resistor AT42QT1481 If Unused, connect To... – Leave open Leave open Leave open Leave open – ...
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... Table 1-1. Pin Listing (Continued) Pin Name 42 Vref S_SYNC / 43 Dbg_Clk 44 SS AT42QT1481 4 Type Comments I Connect to ground O Scope Synchronization output or Debug Clock SPI slave select; has internal 20 k – 50 k pull-up I resistor If Unused, connect To... – Leave open Leave open 9621B–AT42–06/11 ...
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... Rs5 Rs4 Rs3 Rs2 Rs1 check the following sections for component values capacitors (Cs0 – Cs5) 10: Sample resistors (Rs0 – Rs5) 11: Matrix resistors (Rx0 – Rx7, Ry0 – Ry5) 14: Power Supply AT42QT1481 Rx6 Rx5 Rx4 Rx2 Rx1 Rx0 Ry0 Cs0 ...
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... Hardware and Functional 2.1 Introduction The AT42QT1481 (QT1481 digital burst mode sensor, designed specifically for matrix layout touch controls; it includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. Only a few external parts are required for operation. The entire circuit can be built within a few square centimeters of single-sided PCB area. CEM-1 and FR1 punched, single-sided materials can be used for the lowest possible cost. The PCB’ ...
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... (Section 5.5 on page 42). Keys that are disabled are eliminated from the scan AT42QT1481 Section 5.9 on page 44) ...
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... Rounded multiple of whole mains periods, this becomes 20 ms (assuming a mains frequency of 50Hz). The worst case response time is then computed as ( line is considered enabled if any key on that X line is enabled line is disabled if all keys on that X line are disabled. AT42QT1481 8 (Section 5.5 on page 42) (Section 5.5 on page 42) Section 5 ...
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... Unlike other QT circuits, the Cs capacitor values on QT1481 have no effect on conversion gain. However, they do affect conversion time. Unused Y lines should be left open. 9621B–AT42–06/11 Figure 2-2. This nonlinearity is caused by excessive voltage shows a defective waveform similar to that of Figure 2-4. Note that the bottom edge of the bottom trace is AT42QT1481 Figure 2-2, but in this case the 9 ...
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... Larger values for Rs also increase conversion time and may reduce the fastest possible key sampling rate, which can impact response time especially with larger numbers of enabled keys. Unused Y lines do not require an Rs resistor. AT42QT1481 10 VCs – Nonlinear During Burst (Burst too long too small, or X-Y transcapacitance too large) ...
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... X line exposure to nearby ground planes or traces) or the Rx resistor needs to be reduced in value (or a combination of both approaches). 9621B–AT42–06/11 (Figure 1-1 on page Figure 2-5. Too short a dwell time causes charge to be 'lost', if there is too much AT42QT1481 5). (Figure 2-5 on Section 5.13 on page 46). 11 ...
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... X-pulse by 25 percent or more. In almost all cases, Ry should be set equal to Rx, which ensures that the charge on the Y line is fully captured into the Cs capacitor. Figure 2-6. AT42QT1481 12 Drive Pulse Roll-off and Dwell Time Lost charge due to X drive ...
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... This can mean that the flux changes from an inert material to one that can absorb moisture and dramatically affect capacitive measurements due to additional leakage currents. If so, the circuit can become erratic and exhibit poor environmental stability. AT42QT1481 13 ...
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... MSYNC = off, SDC = 0 and STS_DEBUG = 0. Table 2-2. Setups (16 pulses) DWELL = 0 (125 ns) FREQ0 = 0 Signal level = 200 counts (64 pulses) DWELL = 15 (9.9 µs) Signal level = 400 counts AT42QT1481 14 Section 6.1 and Section 6.2 on page Table 2-2 Keyscan Cycle and Calibration Times Keyscan Cycle Time ...
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... The net effect of this mechanism is a multiplication of the inner and outer counters and hence a highly noise-resistant sensing method. If the inner limit is set to 5, and the outer to 3, the net effect successive threshold crossings to declare a key as active. 9621B–AT42–06/11 Section 5.5 on page 42. AT42QT1481 15 ...
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... The FMEA testing is done on all enabled keys in the matrix, and results are reported via the serial interface. Disabled keys are not tested. Assuming no detect events occur, the real time that elapses from the start of one sequence of FMEA tests to the start of the next, or the FMEA sequence time, never exceeds 2s. AT42QT1481 16 , Section 5.14 on page 46 ...
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... The FMEA error flag, LSL error flag and Setups CRC error flag must all be considered as part of an EN60730 compliant design. 9621B–AT42–06/11 Section 5.19 on page 48) 48). If any signal level falls below this level, an error flag is generated. 28) to verify correct operation of the QT1481. The host must also perform Section 4.7 on page AT42QT1481 28) and verify there are no errors 17 ...
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... FREQ0 and FREQ1. CFO_2 indicates the offset to be applied when the frequency is changed between those defined by FREQ0 and FREQ2. The QT1481 uses combinations of these offset values, as necessary, when switching between the three different frequencies. AT42QT1481 18 Section 2.13 on page 14). ...
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... It maintains two such counters, one for positive deltas and one for negative deltas. The QT1481 considers a frequency hop only if both these counters reach the noise integrator limit (NIL). The counters are reset to zero at the end of each matrix scan. The QT1481 will not switch the frequency during calibration. 9621B–AT42–06/11 AT42QT1481 19 ...
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... DRDY is an open-drain output (in SPI mode) or bidirectional pin (in UART mode) with an internal 20 k – 50 k pull-up resistor. Most communications failures are the result of failure to properly observe the DRDY timing. AT42QT1481 20 Section 4.7 on page 28)) in most situations. Streaming commands like the 0x0D Section 4 ...
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... MISO – Master in / Slave out data pin; used as an output for data to the host. This pin should be connected to the MISO (DI) pin of the host. MISO floats in three-state mode between bytes when SS is high to facilitate multiple devices on one SPI bus. 9621B–AT42–06/11 AT42QT1481 Figure 3-2 on page <20 ms < µ ...
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... SPI clocking or false data. Simple RC networks and slower data rates are helpful to resolve these issues. A CRC is appended to responses in order to detect transmission errors to a high level of certainty. AT42QT1481 22 Important: SCK must idle high; it should never float. 9621B–AT42–06/11 ...
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... S5: <100 µs S6: >1 µs S7: >125 {optional 2nd command byte} S4 3-state ? Section 5.17 on page 48. AT42QT1481 QT1481 DRDY SS SCK MISO MOSI S4: <20 ns S8: >125 ns S9: >250 {null byte or next command to get QT response} ...
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... DRDY goes low. Sampling of DRDY by the host should occur 100 µs after the byte has been fully sent. If DRDY is already high at this point, or becomes high, then it is clear to send. AT42QT1481 24 Communications Signals – UART ...
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... SPI or UART serial interfaces. The Debug interface provides a useful aid during product development (see 9621B–AT42–06/11 UART Timing U1: <=100 µs U2, U3: See text * Floats high Section B on page 65). AT42QT1481 Figure 3-4 on page 25. Delay Section 3.5. U4: <=10 µs * Floats high U4 * Stop bit 25 ...
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... In SPI communications, when the QT1481 responds to a command with one or more response bytes, the host can issue a new command instead of a null on the last byte shift operation. New commands during intermediate byte shift-out operations are ignored, and null bytes should always be used. AT42QT1481 26 Table 4-5 on page 36 for further details. ...
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... This command takes seconds to complete. The host can monitor the progress of the calibration by checking the QT1481 status byte, using command 0x06, during the course of the calibration. The calibration bit will be set throughout the process. 9621B–AT42–06/11 AT42QT1481 Section 4.6 on page 28. 27 ...
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... This command returns five individual data bytes, plus two CRC bytes, in the sequence: 1. Device Status 2. Touch Overview 3. 100 ms Counter (for EN60730 compliance) 4. Matrix Scan Counter (for EN60730 compliance) 5. Signal Fail Counter (for EN60730 compliance) A 16-bit CRC is appended to the response; this CRC folds in the command 0x06 itself initially. AT42QT1481 28 28). 9621B–AT42–06/11 ...
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... Any key in calibration Reserved Section 5.14 on page Section 5.18 on page 48). Key Touch Information Description touched keys key in detect keys in detect more keys in detect Number of 1st key declaring detect (0 – 47) AT42QT1481 Table 4-1 on page 29. Section 2.17 on page 16. Section 5.31 on page 53) and 46. This condition is not 29 ...
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... The Matrix Scan count rate can be calculated directly from this. For example, if the keyscan cycle time is measured as 10 ms, the counter counts 256 steps in 2560 ms (256 x 10 ms). The host must read this counter regularly to check the matrix scan is operating at the expected rate. AT42QT1481 30 9621B–AT42–06/11 ...
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... Bit Fields for Multiple Key Reporting and Key Numbering and Table 5-5 on page 55. Section 5.18 on page AT42QT1481 for STS_TOUCH in the STS Bit Number (X Line Number ...
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... This command returns 5 data bytes, plus two CRC bytes, in the sequence: Signal Reference Normal Detect Integrator Signal and Reference are returned LSByte first. A 16-bit CRC is appended to the response. This CRC folds in the command 0x4k itself initially. AT42QT1481 32 Section 5 on page for details of the sleep behavior. 2 bytes 2 bytes 1 byte 39), otherwise this 9621B– ...
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... Status for Key “k” Description 1 = Reserved 1 = Reserved 1 = Reserved 1 = FMEA KGTT test failed for this key 1 = Key is in detect 1 = Signal ref < LSL (low signal error). See 1 = Key is undergoing calibration 1 = Calibration on this key failed AT42QT1481 Table 4-4: Section 5.18 on page 48. Figure 4-1 on page 35 is suggested. 33 ...
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... CRC error in the EEPROM setups at this point is clearly a critical error that would require reloading. This happens at the factory, during the very first power-up cycle. The “Last Com mand” command can be used at any time to resynchronize failed communications, for example due to timing errors. AT42QT1481 34 9621B–AT42–06/11 ...
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... Only 1 Key in Detect 0x07 Report all detections Keys OK Key Detection(s) Processing Stuck Key Detected Done 0xck Cal Key 'k' AT42QT1481 0x01 Load Setups Force Reset Block Any Error Flag, or EN60730 counter sequence error EEPROM CRC error, or calibration fail, or FMEA fail, or multiple errors ...
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Table 4-5. Command Summary Hex Name Description 0x00 Null command Used to get data back in SPI mode Enter Setups, stop sensing; followed by block load of binary Setups of length ‘nn’. Command must be repeated twice consecutively without 0x01 ...
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Table 4-5. Command Summary (Continued) Hex Name Description Device status, indication of first key 0x06 QT1481 Overview touched, EN60730 counters. Sends back all key detect status bits 0x07 Report all keys (bit-field) 0x0B Error flags for all Error bit fields ...
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Table 4-5. Command Summary (Continued) Hex Name Description Get signal, ref, Norm DI for key k {0 – 47} 0x4k Data for 1 key Signal: 2 bytes; Ref: 2 bytes; Norm DI: 1 byte 0x8k Status for key ‘k’ Get ...
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... Typical values: Default value: 9621B–AT42–06/11 Table 5-4 on page 54 for a list of all Setups. shows all translation values. and also Section 5.2 on page counts of threshold internally added to NTHR to generate the threshold). 6 (10 counts of threshold) AT42QT1481 (Threshold Multiplier – THRM) 39 ...
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... The rate of adjustment must be performed slowly, otherwise legitimate detections could be ignored. The QT1481 drift compensates using a slew-rate limited change to the reference level; the threshold and hysteresis values are slaved to this reference. AT42QT1481 40 Table 5-1 Extended Detect Threshold ...
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... Thresholds and Drift Compensation Reference Hysteresis Threshold Signal Output 3.3 seconds per count of drift compensation translation via LUT, page 10 (2.5s / count of drift compensation 3.3 seconds per count of drift compensation; translation via LUT, 10 (2.5s / count of drift compensation) AT42QT1481 57) page 57) 41 ...
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... See Section 2 on page This function is programmed on a per-key basis. Do not use FDIL = 0 because it is invalid. NDIL Typical values: NDIL Default value: FDIL Typical values: FDIL Default value: AT42QT1481 ...
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... DIM. Extended Detect Integrator Limit Multiplier 255 is an illegal number to use (10s to 30s) 20 (10s) 0 – 254 (, 0.5s – 127s) AT42QT1481 Table 5-7 on page 57. Extended Integrator Limit 1 – – – – 120 43 ...
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... This feature assists in solving the problem of surface moisture which can bridge a key touch to an adjacent key, causing multiple key presses. This feature is also useful for panels with tightly spaced keys, where a fingertip might inadvertently activate an adjacent key. AT42QT1481 (0.7s to 2.0s second) 0 – ...
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... SSYNC Bits Scope Sync Output When Burst On... STS_DEBUG shares the use of Pin 43 with SSYNC, but only one feature should be enabled at a time. To prevent interference, all SSYNC bits should be set to zero (Off) if Debug output is desired. 0 (Off) AT42QT1481 5-3). Table 5-3. 45 ...
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... To suppress this problem the WS input allows bursts to synchronize to the noise source. This same input can also be used to wake the part from a low-power Sleep state. The noise sync operating mode is set by parameter MSYNC in Setups. AT42QT1481 (6.25 percent, 12.5 percent) 1 (12.5 percent ...
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... NDRIFT and PDRIFT. 9621B–AT42–06/11 0 (Off (Off, On) Section 5.4 on page 40 Sleep, NDRIFT and PDRIFT. AT42QT1481 Section 2.13 on page 14. Table 5-8 on page 58. 47 ...
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... Key Gain Test Threshold (KGTT). The following equation must hold for the test to pass: Disabled keys are not tested. The Key Gain Test Threshold can be configured to a value between 4 and 64, via LUT (see Table 5-8 on page Limit. AT42QT1481 48 Table 5-7 on page 0 (9600 baud) Section 4.7 on page 28 and Section 4 ...
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... The reset pulse should be allowed to complete before the host sends commands to the QT1481. If commands are received from the host while STATUS is low, STATUS will remain low until the commands stop and the 2s internal host reset timer is allowed to fully cycle. AT42QT1481 Section B on page 65), the QT1481 49 ...
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... This function is programmed on a global basis. DHT default value: 11 (9s) DHT range: 0 – 15 (100 ms – 25.4s) AT42QT1481 50 If the sleep feature has been disabled, the QT1481 never sleeps and the AWAKE setup has no effect. The AWAKE period can be configured to one of 16 values between 100 ms and 25 ...
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... Table 5-7 on page 1 = Calibrate all keys after hop 0 – off 1 = Calibrate all keys after hop 2 = Adjust each key's reference during hop) Table 5-7 on page 24 (delay cycles) 0 – 63 (Highest frequency to Lowest frequency) Table 5-7 on page 30 (delay cycles) 0 – 63 (Highest frequency to Lowest frequency) AT42QT1481 57. 57. 57. 51 ...
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... The following explanation assumes that FREQ0 defines the highest frequency, for convenience of this discussion, but that does not need to be the case. AT42QT1481 52 Table 5-7 on page 36 (delay cycles) 0 – ...
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... negative, set Diff(k, f0, f1) to zero) Diff(k, f0, f2) = Ref(k, f0) - Ref(k, f2) (this value will nearly always be positive negative, set Diff(k, f0, f1) to zero) Appendix AT42QT1481 A. The low order byte should be sent first. (Section 4.3 on page Table 5-7 on page 57 27) ...
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Table 5-4. Setups Block Byte Parameter Symbol Bytes Valid Range Neg threshold NTHR NTHR = 0 – Pos Threshold PTHR PTHR = 0 – 15 Neg Drift Comp NDRIFT NDRIFT = 0 – Pos ...
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Table 5-4. Setups Block Byte Parameter Symbol Bytes Valid Range Frequency 0 FREQ0 343 1 Freq.Hop Mode FHM Detect Integrator DIM Multiplier 344 1 FREQ1 Frequency 1 345 Frequency 2 FREQ2 1 Noise Threshold NSTHR 346 1 Noise Integrator NIL ...
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Key Mapping Some commands return bit-fields related to keys. For example, command 0x07 (report all keys) returns 6 bytes containing flag bits, one per key, to indicate which keys are reporting touches. Table 5-6 The key number is related ...
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Setups Block Summary Table 5-7. Setups Block Summary – Per Key Settings NTHR PTHR NDRIFT Index Counts Counts Secs ...
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Table 5-8. Setups Block Summary – Global Settings DWELL Index RIB NHYST SDC MSYNC µs baud Global 0 - Off - 6.25% - Off - - Off - 0.13 -9,600 -12.5 0.19 - 19,200 2 ...
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... Vdd-0.7 – – – – ±1 – – – 60 AT42QT1481 Units Notes mA µ 4mA sink source µA bits k DRDY, SS, TX, STATUS pins k 59 ...
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... MISO S2 Last CLK to SS S3 SS to 3-state MISO S4 SS to falling DRDY S5 S6 DRDY low pulse width S7 CLK low pulse width S8 CLK high pulse width S9 CLK period Fck SPI Clock rate AT42QT1481 60 Min Typ Max Units 125 125 125 250 4 Notes ns ...
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... Orchard Parkway San Jose, CA 95131 R 9621B–AT42–06/11 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT42QT1481 A2 A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A – – A1 0.05 – ...
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... Marking Either part marking may be used. They are functionally identical. Abbreviation of Part QT1481-AU AT42 Abbreviation of Part QT1481-AU AT42 AT42QT1481 62 Pin 1 ID QT1481 Number AU 6R0 ©ATMEL Date Code Description YWW=programmed externally WW week code number 1-52 Y year code letter 1-26 where: A=2001...J=2010 ...Z=2026 Pin 1 ID ...
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... The part number comprises Atmel 42 = Touch Business Unit QT = Charge-transfer technology 1481 = type of chip and number of channels AU = TQFP chip 6.8 Moisture Sensitivity Level (MSL) 9621B–AT42–06/11 Description 44-pin TQFP RoHS compliant IC MSL Rating Peak Body Temperature MSL3 260 AT42QT1481 Specifications o C IPC/JEDEC J-STD-020 63 ...
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... A CRC calculator for Microsoft Windows is available free of charge from Atmel. AT42QT1481 64 back into the call parameter crc // loop 8 times { crc= (crc << 0x1021; } else { crc= crc << ...
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... Time remaining before host reset pulse is issued at STATUS pin. Each count Time remaining until normal drift compensation is resumed. Each count is 100 ms 11 Time remaining before QT1481 tries to sleep (if enabled). Each count is 100 ms AT42QT1481 Table B-1 shows the Debug Pin 43 (Dbg_Clk) Pin 40 (Dbg_Data) ...
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... AT42QT1481 66 Debug Output Data Frame Description Time remaining before the current SPI or UART command times out. Each count Time remaining before the wait for the next MSYNC signal times out. Each count is ...
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... Test pattern currently being used for various internal EN60730 tests Key gain test sample taken on Y0 Key gain test sample taken on Y1 Key gain test sample taken on Y2 Key gain test sample taken on Y3 Key gain test sample taken on Y4 Key gain test sample taken on Y5 AT42QT1481 67 ...
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... Table B-3. Offset Within Data Set AT42QT1481 68 Format of Data Set for One Key Description Bits 12 – 0: Signal Bits 15 – 13: Calibration Pending 1 – – progress 5 = Success 6 = Failed Bits 12 – 0: Reference Bit 13: 1= LSL fail 3 – 2 Bit 14: 1= Detect Bit 15: 1= KGTT FMEA fail ...
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... Key Design ......................................................................................................13 2.11 PCB Layout, Construction ...............................................................................13 2.11.1 Overview .....................................................................................13 2.11.2 LED Traces and Other Switching Signals ...................................13 2.11.3 PCB Cleanliness .........................................................................13 2.12 Power Supply Considerations .........................................................................14 2.13 Startup/Calibration Times ................................................................................14 2.14 Reset Input ......................................................................................................15 2.15 Detection Integrators .......................................................................................15 2.16 Sleep ...............................................................................................................16 2.17 FMEA Tests .....................................................................................................16 2.18 EN60730 Compliance ......................................................................................17 2.19 Frequency Hopping .........................................................................................18 3.1 Introduction ......................................................................................................20 3.2 DRDY Pin ........................................................................................................20 3.3 SPI Communications .......................................................................................21 3.4 UART Communications ...................................................................................23 3.5 Debug Output Interface ...................................................................................25 AT42QT1481 69 ...
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... Control Commands ................................................................................ 26 5 Setups ..................................................................................................... 39 AT42QT1481 70 4.1 Introduction ......................................................................................................26 4.2 Null Command – 0x00 .....................................................................................26 4.3 Enter Setups Mode – 0x01 ..............................................................................27 4.4 Low Level Cal and Offset – 0x02 .....................................................................27 4.5 Cal All – 0x03 ..................................................................................................28 4.6 Force Reset – 0x04 .........................................................................................28 4.7 QT1481 Overview – 0x06 ................................................................................28 4.8 Report Detections for All Keys – 0x07 .............................................................31 4.9 Report Error Flags for All Keys – ...
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... Calibrated Frequency Offset – CFO_1 and CFO_2 ........................................52 5.30 Setups CRC – SCRC ......................................................................................53 5.31 Setups Block ....................................................................................................53 5.32 STS Bits ...........................................................................................................55 5.33 Key Mapping ....................................................................................................56 5.34 Setups Block Summary ..................................................................................57 6.1 Absolute Maximum Specifications ...................................................................59 6.2 Recommended Operating Conditions .............................................................59 6.3 DC Specifications ............................................................................................59 6.4 Timing Specifications ......................................................................................60 6.5 Mechanical Dimensions ...................................................................................61 6.6 Marking ............................................................................................................62 6.7 Part Number ....................................................................................................62 6.8 Moisture Sensitivity Level (MSL) .....................................................................62 16-bit CRC Algorithm ....................................................... 63 DEBUG Output .................................................................. 64 AT42QT1481 71 ...
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... Associated Documents • Touch Sensors Design Guide Revision History Revision No. Revision A – December 2010 Revision B – June 2011 AT42QT1481 72 History Initial release of datasheet for chip revision 4.0 Datasheet updated for chip revision 6.0 Command 0x02 added Frequency hopping updated NVT removed ...
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... Notes 9621B–AT42–06/11 AT42QT1481 73 ...
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... Literature Requests www.atmel.com/literature ® , Atmel logo and combinations thereof, Adjacent Key Suppression ™ and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) 3-3523-3551 Fax: (+81) 3-3523-7581 Sales Contact www ...